ZHCSMQ8E june   2006  – october 2020 SN65LVDS302

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Input Electrical Characteristics
    7. 6.7  Output Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Device Power Dissipation
    11.     Typical Characteristics
  8. 7 Parameter Measurement Information
    1.     20
    2. 7.1 Power Consumption Tests
    3. 7.2 Typical IC Power Consumption Test Pattern
    4. 7.3 Maximum Power Consumption Test Pattern
    5. 7.4 Output Skew Pulse Position and Jitter Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Swap Pin Functionality
      2. 8.3.2 Parity Error Detection and Handling
    4. 8.4 Device Functional Modes
      1. 8.4.1 Deserialization Modes
        1. 8.4.1.1 1-Channel Mode
        2. 8.4.1.2 2-Channel Mode
        3. 8.4.1.3 3-Channel Mode
      2. 8.4.2 Powerdown Modes
        1. 8.4.2.1 Shutdown Mode
        2. 8.4.2.2 Standby Mode
      3. 8.4.3 Active Modes
        1. 8.4.3.1 Acquire Mode (PLL Approaches Lock)
        2. 8.4.3.2 Receive Mode
      4. 8.4.4 Status Detect and Operating Modes Flow
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Information
      2. 9.1.2 Preventing Increased Leakage Currents in Control Inputs
      3. 9.1.3 Calculation Example: HVGA Display
      4. 9.1.4 How to Determine Interconnect Skew and Jitter Budget
      5. 9.1.5 F/S Pin Setting and Connecting the SN65LVDS302 to an LCD Driver
      6. 9.1.6 How to Determine the LCD Driver Timing Margin
      7. 9.1.7 Typical Application Frequencies
    2. 9.2 Typical Applications
      1. 9.2.1 VGA Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power-Up and Power-Down Sequences
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Dual LCD-Display Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 Community Resource
    2. 12.2 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

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9.1.7 Typical Application Frequencies

The SN65LVDS302 supports pixel clock frequencies from 4 MHz to 65 MHz over 1, 2, or 3 data lanes. Table 9-1 provides a few typical display resolution examples and shows the number of data lanes necessary to connect the SN65LVDS302 with the display. The blanking overhead is assumed to be 20%. Often, blanking overhead is smaller, resulting in a lower data rate. Furthermore, the examples in the table assumes a display frame refresh rate of 60 Hz. The actual refresh rate may differ depending on the application-processor clock implementation.

Table 9-1 Typical Application Data Rates and Serial Lane Usage
DISPLAY SCREEN RESOLUTIONVISIBLE PIXEL COUNTBLANKING OVERHEADDISPLAY REFRESH RATEPIXEL CLOCK FREQUENCY [MHz]SERIAL DATA RATE PER LANE
1-ChM2-ChM3-ChM
176x220 (QCIF+)38,72020%90 Hz4.2 MHz125 Mbps
240x320 (QVGA)76,80020%60 Hz5.5 MHz166 Mbps
640x200128,00020%60 Hz9.2 MHz276 Mbps138 Mbps
352x416 (CIF+)146,43220%60 Hz10.5 MHz316 Mbps158 Mbps
352x440154,88020%60 Hz11.2 MHz335 Mbps167 Mbps
320x480 (HVGA)153,60020%60 Hz11.1 MHz332 Mbps166 Mbps
800x250200,00020%60 Hz14.4 MHz432 Mbps216 Mbps
640x320204,80020%60 Hz14.7 MHz442 Mbps221 Mbps
640x480 (VGA)307,20020%60 Hz22.1 MHz332 Mbps221 Mbps
1024x320327,68020%60 Hz23.6 MHz354 Mbps236 Mbps
854x480 (WVGA)409,92020%60 Hz29.5 MHz443 Mbps295 Mbps
800x600 (SVGA)480,00020%60 Hz34.6 MHz346 Mbps
1024x768 (XGA)786,43220%60 Hz56.6 MHz566 Mbps