ZHCSMQ8E june   2006  – october 2020 SN65LVDS302

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Input Electrical Characteristics
    7. 6.7  Output Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Device Power Dissipation
    11.     Typical Characteristics
  8. 7 Parameter Measurement Information
    1.     20
    2. 7.1 Power Consumption Tests
    3. 7.2 Typical IC Power Consumption Test Pattern
    4. 7.3 Maximum Power Consumption Test Pattern
    5. 7.4 Output Skew Pulse Position and Jitter Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Swap Pin Functionality
      2. 8.3.2 Parity Error Detection and Handling
    4. 8.4 Device Functional Modes
      1. 8.4.1 Deserialization Modes
        1. 8.4.1.1 1-Channel Mode
        2. 8.4.1.2 2-Channel Mode
        3. 8.4.1.3 3-Channel Mode
      2. 8.4.2 Powerdown Modes
        1. 8.4.2.1 Shutdown Mode
        2. 8.4.2.2 Standby Mode
      3. 8.4.3 Active Modes
        1. 8.4.3.1 Acquire Mode (PLL Approaches Lock)
        2. 8.4.3.2 Receive Mode
      4. 8.4.4 Status Detect and Operating Modes Flow
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Information
      2. 9.1.2 Preventing Increased Leakage Currents in Control Inputs
      3. 9.1.3 Calculation Example: HVGA Display
      4. 9.1.4 How to Determine Interconnect Skew and Jitter Budget
      5. 9.1.5 F/S Pin Setting and Connecting the SN65LVDS302 to an LCD Driver
      6. 9.1.6 How to Determine the LCD Driver Timing Margin
      7. 9.1.7 Typical Application Frequencies
    2. 9.2 Typical Applications
      1. 9.2.1 VGA Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power-Up and Power-Down Sequences
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Dual LCD-Display Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 Community Resource
    2. 12.2 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

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8.4.1.2 2-Channel Mode

While LS0 is held high and LS1 is held low, the SN65LVDS302 receives payload data over two SubLVDS data pairs, D0 and D1. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of 15. The internal high speed clock is used to shift in the data payload on D0 and D1 and to deserialize 15 bits of data from each pair. Figure 8-5 illustrates the timing and the mapping of the data payload into the 30-bit frame. The internal high speed clock is divided by a factor of 15 to recreate the pixel clock, and the data payload with pixel clock is presented on the output bus. The reserved bits and parity bit are not output. While in this mode the PLL can lock to a clock that is in the range of 8 MHz through 30 MHz.

GUID-97A0D10A-FAE8-4ACF-945D-F4EC78D89C18-low.gifFigure 8-5 Data and Clock Input in 2-ChM (LS0 = high; LS1 = low)