ZHCSMQ8E june 2006 – october 2020 SN65LVDS302
PRODUCTION DATA
While LS0 is held low and LS1 is held high the SN65LVDS302 receives payload data over three SubLVDS data pairs: D0, D1, and D2. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of 10. The internal high speed clock is used to shift in the data payload on D0, D1, and D2, and to deserialize 10 bits of data from each pair. Figure 8-6 illustrates the timing and the mapping of the data payload into the 30-bit frame. While in this mode the PLL can lock to a clock that is in the range of 20 MHz through 65 MHz.