ZHCSMQ8E june   2006  – october 2020 SN65LVDS302

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Input Electrical Characteristics
    7. 6.7  Output Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Device Power Dissipation
    11.     Typical Characteristics
  8. Parameter Measurement Information
    1.     20
    2. 7.1 Power Consumption Tests
    3. 7.2 Typical IC Power Consumption Test Pattern
    4. 7.3 Maximum Power Consumption Test Pattern
    5. 7.4 Output Skew Pulse Position and Jitter Performance
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Swap Pin Functionality
      2. 8.3.2 Parity Error Detection and Handling
    4. 8.4 Device Functional Modes
      1. 8.4.1 Deserialization Modes
        1. 8.4.1.1 1-Channel Mode
        2. 8.4.1.2 2-Channel Mode
        3. 8.4.1.3 3-Channel Mode
      2. 8.4.2 Powerdown Modes
        1. 8.4.2.1 Shutdown Mode
        2. 8.4.2.2 Standby Mode
      3. 8.4.3 Active Modes
        1. 8.4.3.1 Acquire Mode (PLL Approaches Lock)
        2. 8.4.3.2 Receive Mode
      4. 8.4.4 Status Detect and Operating Modes Flow
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Information
      2. 9.1.2 Preventing Increased Leakage Currents in Control Inputs
      3. 9.1.3 Calculation Example: HVGA Display
      4. 9.1.4 How to Determine Interconnect Skew and Jitter Budget
      5. 9.1.5 F/S Pin Setting and Connecting the SN65LVDS302 to an LCD Driver
      6. 9.1.6 How to Determine the LCD Driver Timing Margin
      7. 9.1.7 Typical Application Frequencies
    2. 9.2 Typical Applications
      1. 9.2.1 VGA Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power-Up and Power-Down Sequences
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Dual LCD-Display Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 Community Resource
    2. 12.2 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

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订购信息

Output Skew Pulse Position and Jitter Performance

The following test patterns are used to measure the output skew pulse position and the jitter performance of the SN65LVDS302. The jitter test pattern stresses the interconnect, particularly to test for ISI, using very long run-lengths of consecutive bits, and incorporating very high and low data rates, maximizing switching noise. Each pattern is self-repeating for the duration of the test.

Table 7-7 Receive Jitter Test Pattern, 1-Channel Mode
WORDTEST PATTERN:
R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE
10x0000001
20x0000031
30x00000F1
40x00003F1
50x0000FF1
60x0003FF1
70x000FFF1
80x0F0F0F1
90x0C30C31
100x0842111
110x1C71C71
120x18C6311
130x1111111
140x3333331
150x2452413
160x22A2A25
170x5555553
180xDB6DB65
190xCCCCCC1
200xEEEEEE1
210xE739CE1
220xE38E381
230xF7BDEE1
240xF3CF3C1
250xF0F0F01
260xFFF0001
270xFFFC001
280xFFFF001
290xFFFFC01
300xFFFFF01
310xFFFFFC1
320xFFFFFF1
Table 7-8 Receive Jitter Test Pattern, 2-Channel Mode
WORDTEST PATTERN:
R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE
10x0000001
20x000FFF3
30x8008001
40x0030037
50xE00E001
60x00FF001
70x007E001
80x003C001
90x0018001
100x1C7E381
110x3333331
120x555AAA5
130x6DBDB61
140x7777771
150x555AAA3
160xAAAAAA5
170x5555553
180xAAA5555
190x8888881
200x9242491
210xAAA5571
220xCCCCCC1
230xE3E1C71
240xFFE7FF1
250xFFC3FF1
260xFF81FF1
270xFE00FF1
280x1FF1FF1
290xFFCFFC3
300x7FF7FF1
310xFFF0007
320xFFFFFF1
Table 7-9 Receive Jitter Test Pattern, 3-Channel Mode
WORDTEST PATTERN:
R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE
10x0000001
20x0000001
30x0000003
40x0101013
50x0303033
60x0707073
70x1818183
80xE7E7E71
90x3535351
100x0202021
110x5454543
120xA5A5A51
130xADADAD1
140x5555551
150xA6A2AA3
160xA6A2AA5
170x5555553
180x5555555
190xAAAAAA1
200x5252521
210x5A5A5A1
220xABABAB1
230xFDFCFD1
240xCAAACA1
250x1818181
260xE7E7E71
270xF8F8F81
280xFCFCFC1
290xFEFEFE1
300xFFFFFF1
310xFFFFFF5
320xFFFFFF5