ZHCSMQ8E june 2006 – october 2020 SN65LVDS302
PRODUCTION DATA
To minimize the power supply noise floor, provide good decoupling near the SN65LVDS302 power pins. TI recommends placing one 0.01-μF ceramic capacitor at each power pin, and two 0.1-μF ceramic capacitors on each power node. The distance between the SN65LVDS302 and capacitors must be minimized to reduce loop inductance and provide optimal noise filtering. Placing the capacitor underneath the SN65LVDS302 on the bottom of the PCB is often a good choice. A 100-pF ceramic capacitor can be put at each power pin to optimize the EMI performance.