(1)Custom temperature ranges available.
The CDCLVP111-SP clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111-SP can accept two clock sources into an input multiplexer. The CDCLVP111-SP is specifically designed for driving 50Ω transmission lines. When an output pin is not used, leaving the pin open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50Ω.
The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin must be connected to CLK0 and bypassed to GND using a 10nF capacitor.
For high-speed performance, the differential mode is strongly recommended.
The CDCLVP111-SP is characterized for operation from –55°C to 125°C.
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 날짜 |
|---|---|---|---|---|
| * | Data sheet | CDCLVP111-SP Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver datasheet (Rev. B) | PDF | HTML | 2025/03/19 |
| * | SMD | CDCLVP111-SP SMD 5962-16207 | 2020/09/22 | |
| * | Radiation & reliability report | CDCLVP111-SP Total Ionizing Dose (TID) Radiation Report (Rev. A) | 2020/01/07 | |
| * | Radiation & reliability report | Single-Event Effects Test Report for CDCLVP111-SP 1:10 LVPECL Clock Distributor | 2017/01/30 | |
| Application brief | DLA Approved Optimizations for QML Products (Rev. C) | PDF | HTML | 2025/06/17 | |
| Application note | Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) | PDF | HTML | 2025/06/10 | |
| Selection guide | TI Space Products (Rev. K) | 2025/04/04 | ||
| More literature | TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) | 2025/02/20 | ||
| Application note | Single-Event Effects Confidence Interval Calculations (Rev. A) | PDF | HTML | 2022/10/19 | |
| E-book | Radiation Handbook for Electronics (Rev. A) | 2019/05/21 |
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PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| CFP (HFG) | 36 | Ultra Librarian |
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PLLatinum Sim 1.6.9.1 installer binary for Windows operating system
PLLatinum Sim 1.6.9.1 software manifest
PLLatinum Sim 1.6.9.1 is a bugfix release to 1.6.9.