LMK3H0102-Q1
- AEC-Q100 Grade 2 qualified for automotive applications
- Ambient temperature: –40°C to 105°C
- Functional Safety-Capable:
- Integrated BAW resonator, no need for external reference
- Flexible frequency generation:
- Two channel dividers: up to three unique output frequencies from 2.5MHz to 400MHz
- LVCMOS outputs supported up to 200MHz: 1.8V, 2.5V, or 3.3V
- Combination of AC-LVDS, DC-LVDS, LP-HCSL, and LVCMOS on OUT0 and OUT1 pins
- Total output frequency stability: ±25ppm
- 2 functional modes: I2C or preprogrammed OTP
- PCIe Gen 1 to Gen 7 compliant: Common Clock with or without SSC, SRNS, and SRIS
- Very low PCIe jitter with SSC:
- PCIe Gen 5 Common Clock jitter: 57.5fs maximum (PCIe limit is 150fs)
- PCIe Gen 6 Common Clock jitter: 34.5fs maximum (PCIe limit is 100fs)
- PCIe Gen 7 Common Clock jitter: 29.6fs maximum (PCIe limit is 67fs)
- Programmable SSC modulation depth
- Preprogrammed: –0.1%, –0.25%, –0.3%, and –0.5% down spread at 200MHz FOD frequency
- Register programmable: –0.1% to –3% down spread or ±0.05% to ±1.5% center spread
- 1.8V to 3.3V supply voltage
- Internal LDOs with –93.1dBc PSNR at 500kHz switching noise for LP-HCSL outputs
- Output-to-output skew: <50ps
- Fail-safe digital input pins
The LMK3H0102-Q1 is a 2-output PCIe Gen 1 to Gen 7 compliant reference-less clock generator with Spread Spectrum Clocking (SSC) support. The part is based on TI proprietary Bulk Acoustic Wave (BAW) technology and provides ±25ppm clock outputs without any crystal or external clock reference. The device can provide two SSC clocks, two non-SSC clocks, or one SSC clock and one non-SSC clock at the same time. The device meets the full PCIe compliance from Gen 1 to Gen 7, including Common Clock with or without SSC, Separate Reference No Spread (SRNS), and Separate Reference Independent Spread (SRIS).
The device can be easily configured through either pins or I2C interface. An external DC/DC can be used to power the device. Refer to Power Supply Recommendations for detailed guidelines on power supply filtering and sourcing from DC/DC.
For OTP default settings for each LMK3H0102Txx configuration, refer to the LMK3H0102 Configuration Guide.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | LMK3H0102-Q1 Reference-Less 2-Differential or 5-Single-Ended Output PCIe Gen 1-7 Compliant Programmable BAW Clock Generator datasheet (Rev. B) | PDF | HTML | 2025. 10. 24 | |
| 애플리케이션 노트 | LMK3H0102-Q1 CISPR-25 and CISPR-32 EMI Report | 2025. 6. 16 | |||
| 애플리케이션 노트 | Clocking Selection Guide for FPD-Link III and FPD-Link IV SerDes | PDF | HTML | 2025. 4. 17 | ||
| 기술 문서 | 쿼츠의 한계를 넘어: BAW 클록이 ADAS 및 IVI 를 재정의하는 방법 | PDF | HTML | Download English Version | 2025. 4. 11 | |
| 기능 안전 정보 | LMK3H0102-Q1 Functional Safety FIT Rate, FMD and Pin FMA | PDF | HTML | 2024. 10. 3 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
LMK3H0102EVM — LMK3H0102 평가 모듈
PLLATINUMSIM-SW — PLL 루프 필터, 위상 잡음, 잠금 시간, 스퍼 시뮬레이션 툴
PLLATINUMSIM-SW는 사용자가 LMX 계열의 위상 고정 루프(PLL) 및 신시사이저를 포함하는 PLLatinum™ 집적 회로의 상세한 설계 및 시뮬레이션을 만들 수 있는 시뮬레이션 툴입니다.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| VQFN (RGT) | 16 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.