LMK1C1106-Q1
- High-performance 1:2, 1:4, 1:6 and 1:8 LVCMOS clock buffer
- Very low output skew:
- LMK1C1102-Q1 and LMK1C1104-Q1
- < 50ps
- LMK1C1106-Q1 and LMK1C1108-Q1
- < 55ps
- LMK1C1102-Q1 and LMK1C1104-Q1
- Extremely low additive jitter:
- LMK1C1102-Q1 and LMK1C1104-Q1
- 7.5fs typical at VDD = 3.3V
- 10fs typical at VDD = 2.5V
- 19.2fs typical at VDD = 1.8V
- LMK1C1106-Q1 and LMK1C1108-Q1
- 12fs typical at VDD = 3.3V
- 15fs typical at VDD = 2.5V
- 28fs typical at VDD = 1.8V
- LMK1C1102-Q1 and LMK1C1104-Q1
- Very low propagation delay < 3ns
- Synchronous output enable
- Supply voltage: 3.3V, 2.5V, or 1.8V
- 3.3V tolerant input at all supply voltages
- Fail-safe inputs
- fmax = 250MHz for 3.3V fmax = 200MHz for 2.5V and 1.8V
- Automotive Grade 1 (–40°C to 125°C)
- AEC-Q100 qualified
- Available in:
- 14 and 16-Pin TSSOP Package
- 8-Pin WSON Package
The LMK1C110x-Q1 is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments. The entire family is designed with a modular approach in mind. Five different fan-out variations, 1:2, 1:4, 1:6 and 1:8 are available.
All family members share the same high performing characteristics such as low additive jitter, low skew, and wide operating temperature range.
The LMK1C110x-Q1 supports a synchronous output enable control (1G) which switches the outputs into a low state when 1G is low. These devices have a fail-safe input that prevents oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.
The LMK1C110x-Q1 family are available in an Automotive Grade 1 (–40°C to 125°C) and AEC-Q100 qualified.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | LMK1C110x-Q1 1.8V, 2.5V, and 3.3V Low Noise LVCMOS Clock Buffer Family datasheet | PDF | HTML | 2026. 3. 25 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
LMK1C1104EVM — LMK1C1104 저지터 1:4 LVCMOS 팬 아웃 버퍼 평가 모듈
PLLATINUMSIM-SW — PLL 루프 필터, 위상 잡음, 잠금 시간, 스퍼 시뮬레이션 툴
PLLATINUMSIM-SW는 사용자가 LMX 계열의 위상 고정 루프(PLL) 및 신시사이저를 포함하는 PLLatinum™ 집적 회로의 상세한 설계 및 시뮬레이션을 만들 수 있는 시뮬레이션 툴입니다.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| TSSOP (PW) | 14 | Ultra Librarian |