Produktdetails

Frequency (max) (MHz) 6400 Frequency (min) (MHz) 28 Normalized PLL phase noise (dBc/Hz) -232 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -124 Features FSK modulation, Flexible ramp generation, Integer-boundary spurs (IBS) removal, Integrated VCO, Phase adjustment, Wideband Current consumption (mA) 75 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
Frequency (max) (MHz) 6400 Frequency (min) (MHz) 28 Normalized PLL phase noise (dBc/Hz) -232 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -124 Features FSK modulation, Flexible ramp generation, Integer-boundary spurs (IBS) removal, Integrated VCO, Phase adjustment, Wideband Current consumption (mA) 75 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
VQFN (RHA) 40 36 mm² 6 x 6
  • Output frequency: 12.5 MHz to 6.4 GHz
  • Low power consumption: 75 mA at 3.3-V supply
  • –106-dBc/Hz Phase noise at 100-kHz offset with 6.4-GHz carrier
  • PLL figure of merit: –232 dBc/Hz
  • PLL normalized 1/f noise: –123.5 dBc/Hz
  • 32-Bit Fractional-N divider
  • Remove integer boundary spurs with programmable input multiplier
  • Synchronization of output phase across multiple devices
  • Support for JESD204B SYSREF with programmable delay
  • Support for ramp and chirp functions
  • Support for FSK direct digital modulation
  • Two programmable output power level differential outputs
  • Fast VCO calibration speed: < 20 µs
  • Single 3-V to 3.5-V power supply
  • Output frequency: 12.5 MHz to 6.4 GHz
  • Low power consumption: 75 mA at 3.3-V supply
  • –106-dBc/Hz Phase noise at 100-kHz offset with 6.4-GHz carrier
  • PLL figure of merit: –232 dBc/Hz
  • PLL normalized 1/f noise: –123.5 dBc/Hz
  • 32-Bit Fractional-N divider
  • Remove integer boundary spurs with programmable input multiplier
  • Synchronization of output phase across multiple devices
  • Support for JESD204B SYSREF with programmable delay
  • Support for ramp and chirp functions
  • Support for FSK direct digital modulation
  • Two programmable output power level differential outputs
  • Fast VCO calibration speed: < 20 µs
  • Single 3-V to 3.5-V power supply

The LMX2572 is a low-power, high-performance wideband synthesizer that can generate any frequency from 12.5 MHz to 6.4 GHz without using an internal doubler. The PLL delivers excellent performance while consuming just 75 mA from a single 3.3-V supply.

For applications like digital mobile radio (DMR) and wireless microphones, the LMX2572 supports FSK modulation. Discrete level FSK and pulse-shaping FSK are supported. Direct digital FSK modulation is achievable through programming or pins.

The LMX2572 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. The LMX2572 provides an option to adjust the phase with fine granularity to account for delay mismatch on the board or within devices. A frequency ramp generator can synthesize up to two segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows the user to change frequencies faster than 20 µs. The LMX2572 also supports generating or repeating SYSREF (compliant to JESD204B standard) making it an ideal low-power, low-noise clock source for clocking high-speed data converters. Fine delay adjustment is provided in this configuration to account for delay differences of board traces.

The LMX2572 integrates LDOs from a single 3.3-V supply, thus eliminating the need for onboard low-noise LDOs.

The LMX2572 is a low-power, high-performance wideband synthesizer that can generate any frequency from 12.5 MHz to 6.4 GHz without using an internal doubler. The PLL delivers excellent performance while consuming just 75 mA from a single 3.3-V supply.

For applications like digital mobile radio (DMR) and wireless microphones, the LMX2572 supports FSK modulation. Discrete level FSK and pulse-shaping FSK are supported. Direct digital FSK modulation is achievable through programming or pins.

The LMX2572 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. The LMX2572 provides an option to adjust the phase with fine granularity to account for delay mismatch on the board or within devices. A frequency ramp generator can synthesize up to two segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows the user to change frequencies faster than 20 µs. The LMX2572 also supports generating or repeating SYSREF (compliant to JESD204B standard) making it an ideal low-power, low-noise clock source for clocking high-speed data converters. Fine delay adjustment is provided in this configuration to account for delay differences of board traces.

The LMX2572 integrates LDOs from a single 3.3-V supply, thus eliminating the need for onboard low-noise LDOs.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Datum
* Data sheet LMX2572 6.4-GHz Low power wideband RF synthesizer with phase synchronization and JESD204B support datasheet (Rev. B) PDF | HTML 29 Jan 2019
Application note Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML 11 Apr 2025
Application brief Compilation of RF Synthesizer Resources PDF | HTML 22 Okt 2024
Application note Sine to Square Wave Conversion Using Clock Buffers PDF | HTML 03 Sep 2024
Circuit design MASH_SEED Optimization and Impact on Spurs (LMX2820) PDF | HTML 08 Aug 2024
Application note Achieving Low Frequency Switchover Time for Wireless Infrastructure Applications 28 Nov 2018
Application note LMX2571 Using a Programmable Input Multiplier to Minimize Integer Boundary Spurs 12 Jan 2016

Design und Entwicklung

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Evaluierungsplatine

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Benutzerhandbuch: PDF
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Support-Software

TICSPRO-SW TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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Designtool

PLLATINUMSIM-SW PLL loop filter, phase noise, lock time, and spur simulation tool

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