CDCLVP2108

Name: CDCLVP2108
Brand: TI
SKU: CDCLVP2108
Price: 9.936 USD

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Jitterarmer Dual-1:8-Universal-zu-LVPECL-Puffer

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Datenblatt

document-pdfAcrobat CDCLVP2108 16-LVPECL Output, High-Performance Clock Buffer datasheet (Rev. C) (Englisch) PDF | HTML

CDCLVP2108

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Datenblatt

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Produktdetails

Number of outputs

16

Additive RMS jitter (typ) (fs)

124

Core supply voltage (V)

2.5, 3.3

Output supply voltage (V)

2.5, 3.3

Output skew (ps)

25

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVPECL

Input type

LVCMOS, LVDS, LVPECL

Number of outputs

16

Additive RMS jitter (typ) (fs)

124

Core supply voltage (V)

2.5, 3.3

Output supply voltage (V)

2.5, 3.3

Output skew (ps)

25

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVPECL

Input type

LVCMOS, LVDS, LVPECL

VQFN (RGZ)

48

49 mm² 7 x 7

Dual 1:8 Differential Buffer
Two Clock Inputs
Universal Inputs Can Accept LVPECL, LVDS,
LVCMOS/LVTTL
16 LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 115 mA
Very Low Additive Jitter: <100 fs, RMS
in 10-kHz to 20-MHz Offset Range
2.375-V to 3.6-V Device Power Supply
Maximum Propagation Delay: 550 ps
Maximum Within Bank Output Skew: 25 ps
LVPECL Reference Voltage, V_{AC_REF},
Available for Capacitive-Coupled Inputs
Industrial Temperature Range: –l40°C
to +85°C
Supports 105°C PCB Temperature (Measured
with a Thermal Pad)
Available in 7-mm × 7-mm, 48-Pin VQFN
(RGZ) Package
ESD Protection Exceeds 2000 V (HBM)

Dual 1:8 Differential Buffer
Two Clock Inputs
Universal Inputs Can Accept LVPECL, LVDS,
LVCMOS/LVTTL
16 LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 115 mA
Very Low Additive Jitter: <100 fs, RMS
in 10-kHz to 20-MHz Offset Range
2.375-V to 3.6-V Device Power Supply
Maximum Propagation Delay: 550 ps
Maximum Within Bank Output Skew: 25 ps
LVPECL Reference Voltage, V_{AC_REF},
Available for Capacitive-Coupled Inputs
Industrial Temperature Range: –l40°C
to +85°C
Supports 105°C PCB Temperature (Measured
with a Thermal Pad)
Available in 7-mm × 7-mm, 48-Pin VQFN
(RGZ) Package
ESD Protection Exceeds 2000 V (HBM)

The CDCLVP2108 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 25 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP2108 clock buffer distributes two clock inputs (IN0, IN1) to 16 pairs of differential LVPECL clock outputs (OUT0, OUT15) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2108 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (V_{AC_REF}) must be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2108 is characterized for operation from –40°C to +85°C and is available in a 7-mm × 7-mm, VQFN-48 package.

The CDCLVP2108 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 25 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP2108 clock buffer distributes two clock inputs (IN0, IN1) to 16 pairs of differential LVPECL clock outputs (OUT0, OUT15) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2108 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (V_{AC_REF}) must be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2108 is characterized for operation from –40°C to +85°C and is available in a 7-mm × 7-mm, VQFN-48 package.

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CDCLVP2108EVM — CDCLVP2108-Evaluierungsmodul

CDCLVP2108EVM is the evaluation module for CDCLVP2108. The CDCLVP2108 is a highly versatile, low additive jitter buffer that integrates two channels of 1:8 LVPECL buffers with selectable LVPECL, LVDS, or LVCMOS inputs. It has a maximum clock frequency up to 2 GHz. The overall additive jitter (...)

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CDCLVP2108

Jitterarmer Dual-1:8-Universal-zu-LVPECL-Puffer

CDCLVP2108

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