The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1204 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1204 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. The CDCLVP1204 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1204 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1204 is characterized for operation from –40°C to +85°C.
| Top-Dokumentation | Typ | Titel | Format-Optionen | Neueste englische Version herunterladen | Datum |
|---|---|---|---|---|---|
| * | Datenblatt | CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer datasheet (Rev. F) | PDF | HTML | 03.09.2015 | |
| Benutzerhandbuch | CDCLVP1204 User's Guide | 09.07.2009 |
Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.
The CDCLVP1204 is a high-performance, low additive phase noise clock buffer. It has two universal input buffers that support either single-ended or differential clock inputs, selectable through a control pin. The device also features on-chip bias generators that can provide the LVPECL common-mode (...)
Der Taktbaum-Architekt ist ein Taktbaum-Synthesetool, das Ihren Designprozess optimiert, indem es Taktbaumlösungen auf der Grundlage Ihrer Systemanforderungen erzeugt. Das Tool zieht Daten aus einer umfangreichen Datenbank von Taktgeberprodukten, um eine Multi-Chip-Taktlösung auf Systemebene zu (...)
PLLATINUMSIM-SW ist ein Simulationstool, mit dem Benutzer detaillierte Designs und Simulationen unserer integrierten PLLatinum™-Schaltkreisen erstellen können, einschließlich der LMX-Serie von phasenverriegelten Schleifen (PLLs) und Synthesizern.
The TIDA-00234 XAUI to SFI reference design is intended for Enterprise and Service Provider Networking applications like Ethernet Switches and Routers that implement multiple 10G Ethernet compliant Optical (SFP+) ports. This reference design features the TLK10232 device which is the most compact (...)
The Gigabit Ethernet Link Aggregator reference design features the TLK10081 device which is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems to reduce the number of physical links by multiplexing lower speed serial links into higher (...)
This verified reference design is a complete four channel DisplayPort aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous DisplayPort (DP) sources together into one 10.8 Gbps serial link. The serial data is transferred via copper or optical fiber where a (...)
This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is (...)
| Gehäuse | Pins | CAD-Symbole, Footprints und 3D-Modelle |
|---|---|---|
| VQFN (RGT) | 16 | Ultra Librarian |
Empfohlene Produkte können Parameter, Evaluierungsmodule oder Referenzdesigns zu diesem TI-Produkt beinhalten.
Inhalte werden ohne Gewähr von TI und der Community bereitgestellt. Sie stellen keine Spezifikationen von TI dar. Siehe Nutzungsbedingungen.
Bei Fragen zu den Themen Qualität, Gehäuse oder Bestellung von TI-Produkten siehe TI-Support.