LMK1D2106

Name: LMK1D2106
Brand: TI
SKU: LMK1D2106
Price: 7.285 USD

AKTIV

6-Kanal-Ausgang Dual-Bank mit 1,8-V-, 2,5-V- und 3,3-V-LVDS-Puffer

Jetzt bestellen

Datenblatt

document-pdfAcrobat LMK1D210x Low Additive Jitter LVDS Buffer datasheet (Rev. A) (Englisch) PDF | HTML

LMK1D2106

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Number of outputs

12

Additive RMS jitter (typ) (fs)

45

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LVDS

Input type

HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL

Number of outputs

12

Additive RMS jitter (typ) (fs)

45

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LVDS

Input type

HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL

VQFN (RHA)

40

36 mm² 6 x 6

High-performance LVDS clock buffer family: up to 2 GHz
- Dual 1:6 differential buffer
- Dual 1:8 differential buffer
Supply voltage: 1.71 V to 3.465 V
Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz
- Very low phase noise floor: -164 dBc/Hz (typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
Bank enable/disable using the EN pin
Fail-safe input operation
Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
LVDS reference voltage, V_{AC_REF}, available for capacitive-coupled inputs
Industrial temperature range: –40°C to 105°C
Packaged in
- LMK1D2106: 6-mm × 6-mm, 40-pin VQFN (RHA)
- LMK1D2108: 7-mm × 7-mm, 48-pin VQFN (RGZ)

High-performance LVDS clock buffer family: up to 2 GHz
- Dual 1:6 differential buffer
- Dual 1:8 differential buffer
Supply voltage: 1.71 V to 3.465 V
Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz
- Very low phase noise floor: -164 dBc/Hz (typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
Bank enable/disable using the EN pin
Fail-safe input operation
Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
LVDS reference voltage, V_{AC_REF}, available for capacitive-coupled inputs
Industrial temperature range: –40°C to 105°C
Packaged in
- LMK1D2106: 6-mm × 6-mm, 40-pin VQFN (RHA)
- LMK1D2108: 7-mm × 7-mm, 48-pin VQFN (RGZ)

The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0 to OUT15) in the LMK1D2108 and 12 pairs of clock outputs (OUT0 to OUT11) in the LMK1D2106 with minimum skew for clock distribution. Each buffer block consists of one input and a maximum of 6 (LMK1D2106) or 8 (LMK1D2108) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D210x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-6).

Using the control pin (EN), output banks can either be enable or disabled. If this pin is left open, both bank outputs are enabled. If the control pin is switched to a logic "0", both bank outputs are disabled (static logic "0"). If the control pin is switched to a logic "1", the outputs of one bank are disabled while the outputs of the other bank are enabled. The part also supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0 to OUT15) in the LMK1D2108 and 12 pairs of clock outputs (OUT0 to OUT11) in the LMK1D2106 with minimum skew for clock distribution. Each buffer block consists of one input and a maximum of 6 (LMK1D2106) or 8 (LMK1D2108) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D210x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-6).

Using the control pin (EN), output banks can either be enable or disabled. If this pin is left open, both bank outputs are enabled. If the control pin is switched to a logic "0", both bank outputs are disabled (static logic "0"). If the control pin is switched to a logic "1", the outputs of one bank are disabled while the outputs of the other bank are enabled. The part also supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

filter

Andere Taktpuffer suchen

Herunterladen Video mit Transkript ansehen Video

Alle anzeigen 1

Top-Dokumentation	Typ	Titel	Format-Optionen	Datum
*	Data sheet	LMK1D210x Low Additive Jitter LVDS Buffer datasheet (Rev. A)	PDF \| HTML	28 Jan 2022

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Evaluierungsplatine

LMK1D1212EVM — LMK1D1212 Jitterarmer 2:12-LVDS-Fanout-Puffer – Evaluierungsmodul

Der LMK1D1212 ist ein hochleistungsfähiger LVDS-Taktpuffer mit geringem additiven Jitter und zwei Differenzeingängen und 12 LVDS-Ausgängen. Dieses Evaluierungsmodul (EVM) dient dazu, die elektrische Leistung des LMK1D1212 zu demonstrieren. Dieses EVM kann auch zur Evaluierung anderer (...)

Benutzerhandbuch: PDF | HTML

Nicht verfügbar auf TI.com

Simulationsmodell

LMK1DX IBIS Model (Rev. B)

SNAM251B.ZIP (67 KB) - IBIS Model

Herunterladen

Designtool

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Unterstützte Produkte und Hardware

Download-Optionen

Simulationstool

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

PSpice® für TI ist eine Design- und Simulationsumgebung, welche Sie dabei unterstützt, die Funktionalität analoger Schaltungen zu evaluieren. Diese Design- und Simulationssuite mit vollem Funktionsumfang verwendet eine analoge Analyse-Engine von Cadence®. PSpice für TI ist kostenlos erhältlich und (...)

Anfordern

Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
VQFN (RHA)	40	Ultra Librarian

Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

LMK1D2106

6-Kanal-Ausgang Dual-Bank mit 1,8-V-, 2,5-V- und 3,3-V-LVDS-Puffer

LMK1D2106

Produktdetails

Ähnliche Produkte, die für Sie interessant sein könnten

Ähnliche Funktionalität wie verglichener Baustein

Technische Dokumentation

Design und Entwicklung

LMK1D1212EVM — LMK1D1212 Jitterarmer 2:12-LVDS-Fanout-Puffer – Evaluierungsmodul

LMK1DX IBIS Model (Rev. B)

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

Unterstützte Produkte und Hardware

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

Bestellen & Qualität

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Videoreihe

Videos

Download-Möglichkeiten

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

Taktpuffer

Taktgeneratoren

Takt-Jitter-Cleaner

Oszillatoren

HF-PLLs und Synthesizer

Hardware-Entwicklung

Dokumentation

Versionsinformationen

Neuheiten