CDCLVD1208

Name: CDCLVD1208
Brand: TI
SKU: CDCLVD1208
Price: 4.555 USD

AKTIV

Jitterarmer 1:8-Universal-auf-LVDS-Puffer mit zwei auswählbaren Eingängen

Jetzt bestellen

Datenblatt

document-pdfAcrobat CDCLVD1208 2:8 Low Additive Jitter LVDS Buffer datasheet (Rev. A) (Englisch) PDF | HTML

CDCLVD1208

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Number of outputs

8

Additive RMS jitter (typ) (fs)

171

Core supply voltage (V)

2.5

Output supply voltage (V)

2.5

Output skew (ps)

45

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVDS

Input type

LVCMOS, LVDS, LVPECL

Number of outputs

8

Additive RMS jitter (typ) (fs)

171

Core supply voltage (V)

2.5

Output supply voltage (V)

2.5

Output skew (ps)

45

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVDS

Input type

LVCMOS, LVDS, LVPECL

VQFN (RHD)

28

25 mm² 5 x 5

2:8 Differential Buffer
Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-MHz
Low Output Skew of 45 ps (Maximum)
Universal Inputs Accept LVDS, LVPECL, and LVCMOS
Selectable Clock Inputs Through Control Pin
8 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
Clock Frequency: Up to 800 MHz
Device Power Supply: 2.375 V to 2.625 V
LVDS Reference Voltage, V_{AC_REF}, Available for Capacitive Coupled Inputs
Industrial Temperature Range: –40°C to 85°C
Packaged in 5-mm × 5-mm, 28-Pin VQFN (RHD)
ESD Protection Exceeds 3-kV HBM, 1-kV CDM
APPLICATIONS
- Telecommunications and Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General-Purpose Clocking

All other trademarks are the property of their respective owners

2:8 Differential Buffer
Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-MHz
Low Output Skew of 45 ps (Maximum)
Universal Inputs Accept LVDS, LVPECL, and LVCMOS
Selectable Clock Inputs Through Control Pin
8 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
Clock Frequency: Up to 800 MHz
Device Power Supply: 2.375 V to 2.625 V
LVDS Reference Voltage, V_{AC_REF}, Available for Capacitive Coupled Inputs
Industrial Temperature Range: –40°C to 85°C
Packaged in 5-mm × 5-mm, 28-Pin VQFN (RHD)
ESD Protection Exceeds 3-kV HBM, 1-kV CDM
APPLICATIONS
- Telecommunications and Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General-Purpose Clocking

All other trademarks are the property of their respective owners

The CDCLVD1208 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The CDCLVD1208 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1208 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage, V_{AC_REF}, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1208 is packaged in small, 28-pin, 5-mm × 5-mm VQFN package.

The CDCLVD1208 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The CDCLVD1208 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1208 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage, V_{AC_REF}, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1208 is packaged in small, 28-pin, 5-mm × 5-mm VQFN package.

filter

Andere Taktpuffer suchen

Herunterladen Video mit Transkript ansehen Video

Alle anzeigen 1

Top-Dokumentation	Typ	Titel	Format-Optionen	Datum
*	Data sheet	CDCLVD1208 2:8 Low Additive Jitter LVDS Buffer datasheet (Rev. A)	PDF \| HTML	31 Okt 2016

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Evaluierungsplatine

CDCLVD1204EVM — CDCLVD1204-Evaluierungsmodul

The CDCLVD1204/CDCLVD2102 are high-performance, low-additive jitter clock buffers. They have twouniversal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1204 only). The devices also feature on-chip bias generators that can (...)

Benutzerhandbuch: PDF

Nicht verfügbar auf TI.com

Simulationsmodell

CDCLVD1208 IBIS Model (Rev. B)

SLLM090B.ZIP (14 KB) - IBIS Model

Herunterladen

Designtool

CLOCK-TREE-ARCHITECT — Programmiersoftware Clock Tree Architect

Der Taktbaum-Architekt ist ein Taktbaum-Synthesetool, das Ihren Designprozess optimiert, indem es Taktbaumlösungen auf der Grundlage Ihrer Systemanforderungen erzeugt. Das Tool zieht Daten aus einer umfangreichen Datenbank von Taktgeberprodukten, um eine Multi-Chip-Taktlösung auf Systemebene zu (...)

Jetzt entwickeln

Designtool

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Unterstützte Produkte und Hardware

Download-Optionen

Simulationstool

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

PSpice® für TI ist eine Design- und Simulationsumgebung, welche Sie dabei unterstützt, die Funktionalität analoger Schaltungen zu evaluieren. Diese Design- und Simulationssuite mit vollem Funktionsumfang verwendet eine analoge Analyse-Engine von Cadence®. PSpice für TI ist kostenlos erhältlich und (...)

Anfordern

Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
VQFN (RHD)	28	Ultra Librarian

Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

CDCLVD1208

Jitterarmer 1:8-Universal-auf-LVDS-Puffer mit zwei auswählbaren Eingängen

CDCLVD1208

Produktdetails

Ähnliche Produkte, die für Sie interessant sein könnten

Selbe Funktionalität wie der verglichene Baustein bei gleicher Anschlussbelegung

Ähnliche Funktionalität wie verglichener Baustein

Technische Dokumentation

Design und Entwicklung

CDCLVD1204EVM — CDCLVD1204-Evaluierungsmodul

CDCLVD1208 IBIS Model (Rev. B)

CLOCK-TREE-ARCHITECT — Programmiersoftware Clock Tree Architect

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

Unterstützte Produkte und Hardware

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

Bestellen & Qualität

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Videoreihe

Videos

Download-Möglichkeiten

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

Taktpuffer

Taktgeneratoren

Takt-Jitter-Cleaner

Oszillatoren

HF-PLLs und Synthesizer

Hardware-Entwicklung

Dokumentation

Versionsinformationen

Neuheiten