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高速 ADC (≥10 MSPS)

ADC31RF80

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14 位 3GSPS 射频采样宽带接收器和反馈集成电路

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ADC31RF80

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产品详情

Sample rate (max) (Msps) 3000 Resolution (Bits) 14 Number of input channels 1 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 1.35 Power consumption (typ) (mW) 3200 Architecture Pipeline SNR (dB) 61.4 ENOB (Bits) 9.8 SFDR (dB) 71 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 3000 Resolution (Bits) 14 Number of input channels 1 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 1.35 Power consumption (typ) (mW) 3200 Architecture Pipeline SNR (dB) 61.4 ENOB (Bits) 9.8 SFDR (dB) 71 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RMP) 72 100 mm² 10 x 10
  • 14-Bit, 3-GSPS ADC
  • Noise Floor: –155 dBFS/Hz
  • RF Input Supports Up To 4.0 GHz
  • Aperture Jitter: 90 fS
  • Spectral Performance (fIN = 900 MHz, –2 dBFS):
    • SNR: 61.4 dBFS
    • SFDR: 71-dBc HD2, HD3
    • SFDR: 76-dBc Worst Spur
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.5 dBFS
    • SFDR: 65-dBc HD2, HD3
    • SFDR: 75-dBc Worst Spur
  • On-Chip Digital Down-Converters:
    • Up to 2 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors With Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Support at 12.5 Gbps
  • Total Power Dissipation: 3.2 W at 3.0 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • 14-Bit, 3-GSPS ADC
  • Noise Floor: –155 dBFS/Hz
  • RF Input Supports Up To 4.0 GHz
  • Aperture Jitter: 90 fS
  • Spectral Performance (fIN = 900 MHz, –2 dBFS):
    • SNR: 61.4 dBFS
    • SFDR: 71-dBc HD2, HD3
    • SFDR: 76-dBc Worst Spur
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.5 dBFS
    • SFDR: 65-dBc HD2, HD3
    • SFDR: 75-dBc Worst Spur
  • On-Chip Digital Down-Converters:
    • Up to 2 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors With Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Support at 12.5 Gbps
  • Total Power Dissipation: 3.2 W at 3.0 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)

The ADC31RF80 device is a 14-bit, 3-GSPS, single-channel telecom receiver and feedback device that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC31RF80 delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

The ADC31RF80 comes with a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC31RF80 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).



The ADC31RF80 device is a 14-bit, 3-GSPS, single-channel telecom receiver and feedback device that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC31RF80 delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

The ADC31RF80 comes with a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC31RF80 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).



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* 数据表 ADC31RF80 3-GSPS Telecom Receiver and Feedback Device 数据表 PDF | HTML 2017年 8月 23日
应用手册 Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B) 2017年 9月 5日

设计与开发

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评估板

ADC32RF80EVM — 适用于 ADC32RF80 双通道、14 位、3GSPS、射频采样宽带接收器的评估模块

ADC32RF80 评估模块 (EVM) 展示了具有 JESD204B 接口的双通道、3GSPS、14 位模数转换器 (ADC) 的性能。该 EVM 包含 ADC32RF80 器件、由 LMK04828 提供的 JESD204B 时钟，以及用于提供必需电压的 TI 稳电压压器。此 ADC 每个通道的输入默认连接到一个变压器输入电路，该电路可连接到 50Ω 单端信号源。

时钟基准输入通过变压器输入提供，而且时钟基准输入可连接到 50Ω 单端时钟源。可使用板载 LMK04828 生成必需的 JESD204B 时钟。

通过板载 USB 连接和基于 Windows® 的 GUI 访问配置寄存器。FMC (...)

用户指南: PDF
TI.com 上无现货
固件

TI204C-IP — Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

支持的产品和硬件

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仿真模型

ADC32RF45 IBIS Model

SBAM273.ZIP (46 KB) - IBIS Model
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仿真模型

ADC32RF45 IBIS-AMI Model

SBAM274.ZIP (3109 KB) - IBIS-AMI Model
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计算工具

FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel Calculator

This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of (...)

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模拟工具

PSPICE-FOR-TI — PSpice® for TI 设计和仿真工具

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。 

在 PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)
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封装 引脚 CAD 符号、封装和 3D 模型
VQFNP (RMP) 72 Ultra Librarian
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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  • 制造厂地点
  • 封装厂地点

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