SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
The SPI can generate interrupts when the following conditions are observed:
All interrupt events are ORed together before being sent to the SVT event fabric, so the SPI generates a single interrupt request regardless of the number of active interrupts. The interrupt conditions listed above can be masked by setting the appropriate bit in the SPI.IMASK register. Setting the appropriate mask bit in the SPI.IMASK register enables the interrupt. SPI.IMSET and SPI.IMCLR are alias registers which can be used to set and clear individual bits of SPI.IMASK register.
The status of the individual interrupt sources can be read from the SPI Raw Interrupt Status register (SPI.RIS) and the SPI Masked Interrupt Status register (SPI.MIS). SPI.ICLR can be used to clear interrupt flags within RIS and MIS. SPI.ISET can be used to set these interrupt flags for debug or test purposes.
The transmit FIFO service interrupt request SPI.RIS[4] TX bit is not gated with the SPI enable signal, which allows data to be written to the transmit FIFO before enabling the SPI by an interrupt service routine (ISR).
The receive FIFO overflow interrupt SPI.RIS[0] RXOVF is asserted when the FIFO is already full and an additional data frame is received, causing an overrun of the FIFO. Data is overwritten in the receive shift register, but not in the FIFO.
The parity error interrupt SPI.RIS[1] PER bit is set when a parity error is detected. SPI.CTL1[5] PEN bit can be written to enable the parity check, where the last bit received is used as parity to test the integrity of the previous bits. SPI.CTL1[7] PBS bit selects the parity mode as even or odd. When a parity fault is detected, the interrupt flag SPI.RIS[1] PER bit is set (to mark the data as invalid).
The idle interrupt SPI.RIS[6] IDLE is set when the SPI transmission has concluded and SPI module moves back to idle mode. This is set when SPI.STA[4] BUSY goes low.
The SPI Receive Timeout interrupt is set when SPI is in peripheral mode and has not been receiving data for the number of functional clock cycles (CLKSVT) configured within SPI.CTL1[29:24] RTOUT bit field. A value of 0 disables this function. The countdown is started when SPI is in the peripheral mode and the first SCLK positive edge is detected and the countdown is restarted on each subsequent SCLK positive edge. A timeout error is asserted if the count reaches zero before the next SCLK toggles.