SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
Table 22-28 lists the memory-mapped registers for the LRFDTXF registers. All register offset addresses not listed in Table 22-28 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | TXD | Data to from TXFIFO | Go |
Complex bit access types are encoded to fit into small table cells. Table 22-29 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
TXD is shown in Table 22-30.
Return to the Summary Table.
TX FIFO data. When written the register data is pushed to the TX FIFO. When read, data is popped from the TX FIFO
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | TX FIFO data. When written the register data is pushed to the TX FIFO. When read, data is popped from the TX FIFO. When writing or reading this register the access size will determine how many bytes are pushed to or popped from the FIFO. It is possible to push or pop 1,2 or 4 bytes depending on the access being done. |