SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
Once the reset pin is deasserted and the minimum supply voltage is supplied, the device enters the ACTIVE power state. HFOSC and the Global LDO are enabled. Once the digital supply is good, the cold boot sequence is performed, applying trims to analog circuitry (including oscillators and voltage regulators) and memories. The CPU boots into the user application at which point the application can configure and enable the DC/DC, low frequency crystal (LFXT) or low frequency oscillator (LFOSC) or high frequency reference clock (HFXT). For more information on the boot process see Chapter 150.
In the ACTIVE power state, both MCU and AON power domains are powered. Clock gating is used to minimize power consumption. Clock gating to peripherals/subsystems is controlled manually by the CPU.