A mechanism to allow ADC to perform
ad-hoc single conversions (ASC) without affecting the scheduled conversions is
provided. The ADC sequencer slots the ASC request at a time when it finds an idle
window in the middle of scheduled conversions without affecting the timing integrity
of the scheduled conversions.
This is requested via CTL3 register
which has fields for specifying the ADC channel number, voltage reference option and
sample period for conversion. Any write to this register is treated as ad-hoc single
conversion request by the sequencer. There is a separate result register available
to store the data for ad-hoc single conversion (ASCRES). This is a dedicated
register for ad-hoc single conversion operation which is different than result
registers/FIFO available to store results from conversion on sensor channels.
Once software writes into ASC configuration register for ad-hoc single conversion
there is a status bit that indicates the ASC is active (ASCACT) and goes low once
the ASC operation is completed.
When the ASC operation is completed, an interrupt flag ASC done (ASCDONE) is set that
can be unmasked by software to read the ASC result in the interrupt service routine.
Software can write into ASC
configuration register at any time in ad-hoc manner and that request is registered
by the sequencer and serviced at a suitable time.
Figure 17-4 shows the ADC sequencer state-machine for ASC operation
Repeat Single Channel Mode and ASC Request
- When the sequencer operates in
repeat single channel with sample trigger policy as auto-next, then the selected
sensor channel is converted back to back continuously and the ASC request is
pended by the sequencer and it is taken up and serviced only when the software
stops repeat single channel conversion. When the sample trigger policy is
trigger-next, then upon ASC request, the sequencer tries to schedule the ASC
operation at the end of ongoing conversion (EOC - End of Conversion).
- It starts ASC operation and will complete it successfully if the scheduled
trigger on sensor channel does not arrive in between.
- If the scheduled trigger is received in the middle of ASC operation, then ASC
conversion is aborted immediately and scheduled conversion is performed.
- If sequencer is not successful in completing ASC operation in the middle of
scheduled conversions, then it will be serviced only when the software stops
repeat single channel conversion.
Sequence of Channels mode and ASC Request
- In the case of sequence of
channels operation with sample trigger policy as auto-next for all channels in
the sequence, the ASC request will be slotted at the end of sequence and
completed.
- If the sample trigger policy is
trigger-next for one or more channels in the sequence, then sequencer tries to
schedule the ASC operation at EOC of channel with trigger next policy set.
- If it can't complete ASC conversion successfully due to arrival of scheduled
trigger then ASC operation is taken up and completed at the end after conversion
of all channels in the sequence are completed.
Repeat Sequence of Channels Mode and ASC Request
- In the case of repeat sequence of
channels operation with sample trigger policy as auto-next for all channels in
the sequence, the ASC request will be slotted and completed when repeat sequence
operation is stopped by software.
- If the sample trigger policy is
trigger-next for one or more channels in the sequence, then sequencer tries to
schedule the ASC operation at EOC of channel with trigger next policy set.
- If it can't complete ASC conversion successfully due to arrival of scheduled
trigger then ASC operation is taken up and completed when the repeat sequence
operation is stopped by software.
ASC Operation Abort Due to Scheduled Trigger
- When the scheduled trigger arrives during the sample phase of ASC operation then
the sequencer pulls the sample signal low immediately and applies reset to ADC
SAR logic and then generates sample trigger for the scheduled conversion.
- When the scheduled trigger arrives during the conversion phase of ASC operation
then sequencer applies reset to ADC SAR logic and then generates sample trigger
for the scheduled conversion.
- When the ASC operation gets aborted due to arrival of scheduled trigger, the
sequencer attempts to perform ASC operation automatically at the next earliest
idle slot without software requiring to re-issue ASC request.
- ASC request is not pipelined which means software has to issue ASC request only
when ASC active status is low.
- If ASC request is raised while
previous ASC operation is not completed then that ASC request is ignored and
software has to reissue ASC request when ASC active is low.