SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
SPI can be configured to controller mode by setting the SPI.CTL1[2] MS bit to 1, and to peripheral mode by clearing the SPI.CTL1[2] MS bit.
The chip select signal needs to be provided by the controller in Motorola 4-wire mode.
SPI includes a feature to keep the CS active low until all data has been transferred from TXFIFO, regardless of the configuration of PHA or POL, in controller mode and Motorola 4-wire frame format. This feature is enabled by the SPI.CTL0[10] HWCSN bit. If SPI.CTL0[14] AUTOCRC is set, then CS is kept low until the CRC has been transferred as well.
In peripheral mode, the clock is provided by the controller and used by the SPI to capture the data. The peripheral has the option to operate in 3-wire or 4-wire mode. 4-wire mode only accepts data transfers if the CS is activated.
When SPI is in peripheral mode and the SPI.CTL0[12] CSCLR bit is set, the receive shift register is cleared automatically when CS goes to inactive state.