SPRUIF3B May   2017  – March 2019 DRA790 , DRA791 , DRA793 , DRA797

 

  1.   DRA79x EVM CPU board
    1.     Trademarks
    2. 1 Introduction
    3. 2 Overview
      1. 2.1 EVM System Configurations
      2. 2.2 CPU Board Feature List
      3. 2.3 CPU Board Component Identification
    4. 3 Hardware
      1. 3.1 Hardware Architecture
      2. 3.2 DRA71x, DRA79x, TDA2E-17, and AM570x Processor
      3. 3.3 Power Architecture
      4. 3.4 Reset Structure
      5. 3.5 Clocks
      6. 3.6 Memory
        1. 3.6.1  SDRAM Memory
        2. 3.6.2  QSPI Flash Memory
        3. 3.6.3  EMMC Flash Memory
        4. 3.6.4  MicroSD Card Cage
        5. 3.6.5  GPMC NOR Flash Memory
        6. 3.6.6  GPMC NAND Flash Memory
        7. 3.6.7  Boot Modes
        8. 3.6.8  JTAG/Emulator and Trace
        9. 3.6.9  UART Terminal
        10. 3.6.10 DCAN and CAN Interfaces
        11. 3.6.11 Universal Serial Bus (USB)
        12. 3.6.12 Wired Ethernet
        13. 3.6.13 Video Output
          1. 3.6.13.1 HDMI Display
          2. 3.6.13.2 LCD Touch Panel
          3. 3.6.13.3 FPD-Link III Output/Panel
        14. 3.6.14 Video Input
          1. 3.6.14.1 Parallel Imaging
          2. 3.6.14.2 Serial Imaging
        15. 3.6.15 Mini-PCIe
        16. 3.6.16 Media Local Bus (MLB)
        17. 3.6.17 Audio
        18. 3.6.18 COM8 Module Interface
        19. 3.6.19 eFuse Programming Supply
        20. 3.6.20 User Interface LEDs
        21. 3.6.21 Power Monitoring
        22. 3.6.22 I2C Peripheral Map
        23. 3.6.23 GPIO List
        24. 3.6.24 I/O Expander List
        25. 3.6.25 Configuration EEPROM
    5. 4 Signal Multiplex Logic
      1. 4.1 GPMC and QSPI Selection (MUX A)
      2. 4.2 GPMC, VIN1, and VOUT3 Selection (MUX B)
      3. 4.3 GPMC and EMMC Selection (MUX C)
      4. 4.4 VIN2A and EMU Selection (MUX D, MUX E)
      5. 4.5 VIN2A and RGMII1 Selection (MUX F)
      6. 4.6 RGMII0 and VIN1B Selection (MUX J)
      7. 4.7 SPI2 and UART3 Selection (MUX K)
      8. 4.8 DCAN2 and I2C3 Selection (MUX L)
    6. 5 USB3 Supported Configurations
      1. 5.1 Option 1
      2. 5.2 Option 2
      3. 5.3 Option 3
    7. 6 References
  2.   Revision History

3.6.7 Boot Modes

The SoC supports a variety of different boot modes, which is determined by the 16-bit system boot setting present on the shared specific I/O balls during power-on sequence (see the TRM for details). Boot mode selection is accomplished by the setting of DIP switches SW3 and SW4, as shown in Table 6, before cycling power.

These SoC resources can be redeployed through both SoC pin EVM MUX settings to support alternate interfaces after boot-up.

Table 6. SoC Boot Mode Switch Settings

SoC Interface
(Internal System Boot Input)		 CPU Board Net DIP Switch Reference Designator Position
Number Connections		 Factory Setting
GPMC_AD0
(sysboot0)		 GPMC_D00 SW3.P1 On
GPMC_AD1
(sysboot1)		 GPMC_D01 SW3.P2 Off
GPMC_AD2
(sysboot2)		 GPMC_D02 SW3.P3 On
GPMC_AD3
(sysboot3)		 GPMC_D03 SW3.P4 Off
GPMC_AD4
(sysboot4)		 GPMC_D04 SW3.P5 On
GPMC_AD5
(sysboot5)		 GPMC_D05 SW3.P6 Off
GPMC_AD6
(sysboot6)		 GPMC_D06 SW3.P7 Off
GPMC_AD7
(sysboot7)		 GPMC_D07 SW3.P8 Off
GPMC_AD8
(sysboot8)		 GPMC_D08 SW4.P1 On
GPMC_AD9
(sysboot9)		 GPMC_D09 SW4.P2 Off
GPMC_AD10
(sysboot10)		 GPMC_D10 SW4.P3 Off
GPMC_AD11
(sysboot11)		 GPMC_D11 SW4.P4 Off
GPMC_AD12
(sysboot12)		 GPMC_D12 SW4.P5 Off
GPMC_AD13
(sysboot13)		 GPMC_D13 SW4.P6 Off
GPMC_AD14
(sysboot14)		 GPMC_D14 SW4.P7 Off
GPMC_AD15
(sysboot15)		 GPMC_D15 SW4.P8 On

In addition to SoC boot settings, EVM resources must also be set for the desired boot interface. Table 7 lists the boot interfaces that require selection. DIP switch SW8 is used to configure the various boot memories.

Table 7. Board Controls for Memory Booting Options

Signals Description DIP Switch Factory Setting
NAND_BOOTn(1) On: Enable GPMC_nCS0 for NAND flash boot SW8.1 Off
NOR_BOOTn(1) On: Enable GPMC_nCS0 for NOR flash boot SW8.2 Off
MMC2_BOOT On: Enable MMC2 Interface for eMMC flash boot SW8.3 Off
Not Used Not Used SW8.4 Off
SW_VPP_EN On: Enable VPP supply to SOC
(also requires I/O expander bit to be set)		 SW8.5 Off
MCASP1_ENn Low: Enable COMx signal paths SW8.6 Off
NOR_ALT_ADDRn Off: Selects default pin location for GPMC ADDR
On: Selects alternate/new pin locations for GPMC		 SW8.7 Off
PCI_RESET_SEL High: PCIe device may reset SoC.
Low: SoC may reset the PCIe device.		 SW8.8 Off
GPMC_WPN Low: Enable write protection of NAND flash SW5.9 Off
I2C_EEPROM_WP High: Enable write protection of board identification EEPROM SW5.10 Off
  1. Routing control for GPMC_nCS0 is shared between the NOR and NAND flash memories. Ensure that only one DIP switch, SW8.P1 or SW8.P2, is ever set to the on state at any time so that GMPC_nCS0 is connected to only one memory. Failure to adhere to this requirement causes NOR and NAND memory data bus contention