SLAAET8A April   2025  – December 2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0C1105 , MSPM0C1106 , MSPM0C1106-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0G3529-Q1 , MSPM0H3216 , MSPM0H3216-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2EMC and EMC Standards
    1. 2.1 EMC
      1. 2.1.1 EMS
      2. 2.1.2 EMI
    2. 2.2 EMC Standards
      1. 2.2.1 EMC Standards Category
    3. 2.3 EMC and IC Electrical Reliability in TI
  6. 3EMC Improvement Guidelines Summary
    1. 3.1 PCB Design Guidelines
    2. 3.2 Firmware Guidelines
  7. 4EMC Improvement Features on MSPM0
    1. 4.1 Susceptibility Protection Features
      1. 4.1.1 POR and BOR
      2. 4.1.2 NMI and Hard Fault
      3. 4.1.3 I/O ESD and Settings
    2. 4.2 Emission Reduction Features
      1. 4.2.1 Clock Source
      2. 4.2.2 Power Modes
      3. 4.2.3 Package
  8. 5Analysis for EMS Test
    1. 5.1 Root Cause Analysis
      1. 5.1.1 Permanent Damage
      2. 5.1.2 Recoverable Malfunction
    2. 5.2 Debug Flow
  9. 6Analysis for EMI Test
    1. 6.1 Root Cause Analysis
      1. 6.1.1 Power Line
      2. 6.1.2 External Vcore
    2. 6.2 Debug Flow
  10. 7Summary
  11. 8References
  12. 9Revision History

4.1.2 NMI and Hard Fault

MSPM0 has two interrupt mechanisms to handle unexpected behaviors from the MCUs, which are useful to analyze the root cause of EMS failure. The first is NMI, which is designed to handle critical system events that require immediate attention. The second is hard fault, which is a nonmaskable exception triggered by severe system errors that cannot be handled by other exception mechanisms.

When NMI happens, users can track the trigger sources by checking the NMI interrupt index and find a valid resolution. An example is shown in Table 4-2.

Table 4-2 MSPM0G Nonmaskable Interrupt Event
Index (IIDX) Name Description
0 NONE No NMI pending.
1 BORLVL Indicates that VDD has dropped below the specified VBOR- threshold.
2 WWDT0 A WWDT0 violation occurred.
3 WWDT1 A WWDT1 violation occurred.
4 LFCLKFAIL Indicates that the LFXT or LFCLK_IN clock source is dead. This indication is useful for handling LFCLK errors when LFCLK is not sourcing MCLK but is sourcing a peripheral (for example, the RTC).
5 FLASHDED Indicates that a flash memory double-bit uncorrectable error was detected.
6 SRAMDED Indicates that an SRAM double-bit uncorrectable error was detected.

Hard fault serves as a last-resort handler for unrecoverable faults, such as memory access errors, unaligned memory operations, execution of undefined or illegal instructions and bus errors. Unlike higher-end Cortex®-M cores (for example, M3 and M4), the M0+ lacks configurable fault status registers (CFSR), making fault analysis more challenging and reliant on manual inspection. Hard fault generate a hard fault interrupt. Users can use this as an assert signal to adjust the system to pass the EMS test.