SLAAET8A April   2025  – December 2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0C1105 , MSPM0C1106 , MSPM0C1106-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0G3529-Q1 , MSPM0H3216 , MSPM0H3216-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2EMC and EMC Standards
    1. 2.1 EMC
      1. 2.1.1 EMS
      2. 2.1.2 EMI
    2. 2.2 EMC Standards
      1. 2.2.1 EMC Standards Category
    3. 2.3 EMC and IC Electrical Reliability in TI
  6. 3EMC Improvement Guidelines Summary
    1. 3.1 PCB Design Guidelines
    2. 3.2 Firmware Guidelines
  7. 4EMC Improvement Features on MSPM0
    1. 4.1 Susceptibility Protection Features
      1. 4.1.1 POR and BOR
      2. 4.1.2 NMI and Hard Fault
      3. 4.1.3 I/O ESD and Settings
    2. 4.2 Emission Reduction Features
      1. 4.2.1 Clock Source
      2. 4.2.2 Power Modes
      3. 4.2.3 Package
  8. 5Analysis for EMS Test
    1. 5.1 Root Cause Analysis
      1. 5.1.1 Permanent Damage
      2. 5.1.2 Recoverable Malfunction
    2. 5.2 Debug Flow
  9. 6Analysis for EMI Test
    1. 6.1 Root Cause Analysis
      1. 6.1.1 Power Line
      2. 6.1.2 External Vcore
    2. 6.2 Debug Flow
  10. 7Summary
  11. 8References
  12. 9Revision History

5.1.1 Permanent Damage

From the data sheet perspective, the abnormal MCU performance is due to going over the specifications. First, is the absolute maximum ratings. If users go over this specification, then permanent damage can happen. An example from MSPM0G3507 is shown in Table 5-2. In EMS tests, the input voltage for common tolerance pins are often not satisfied and causes damage to MSPM0 when the emission noise is injected into MSPM0 through IO pins. Another issue is the constant diode current specification. This is the current limit beyond which the ESD diode turns ON and starts clamping the voltage. If the ESD diode current is not allowed, like PA24 in MSPM0C1104, then this means the ESD diode starts clamping the voltage at the beginning.

Table 5-2 Absolute Maximum Ratings of MSPM0G
PARAMETER(1)TEST CONDITIONS(2)MINMAXUNIT
VDDSupply voltageAt VDD pin–0.34.1V
VIInput voltageApplied to any 5V tolerant open-drain pins–0.35.5V
VIInput voltageApplied to any common tolerance pins–0.3VDD + 0.3 (4.1 MAX)V
IVDDCurrent into VDD pin (source)-40℃ ≤ Tj ≤ 130℃ 80mA
Current into VDD pin (source)-40℃ ≤ Tj ≤ 85℃100mA
IVSSCurrent out of VSS pin (sink)-40℃ ≤ Tj ≤ 130℃ 80mA
Current out of VSS pin (sink)-40℃ ≤ Tj ≤ 85℃100mA
IIOCurrent of SDIO pinCurrent sunk or sourced by SDIO pin6mA
Current of HS_IO pinCurrent sunk or sourced by HSIO pin6mA
Current of HDIO pinCurrent sunk or sourced by HDIO pin20mA
Current of ODIO pinCurrent sunk by ODIO pin20mA
IDSupported diode currentDiode current at any device pin±2 (3)mA
(1) Stresses beyond those listed under Absolute Maximum Rating can cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.
(2) Higher temperatures can be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
(3) PA21 has an internal connection for testing purposes; there is no injection current allowed on this pin.

The second is the recommended operating conditions. If MSPM0 goes over this specification, then recoverable malfunction can happen. Therefore, the capacitor usages are suggested to follow the instructions.

Table 5-3 Recommended Operating Conditions
(3)MINNOMMAXUNIT
VDDSupply voltage1.623.6V
VCOREVoltage on VCORE pin (2)1.35V
CVDDCapacitor connected between VDD and VSS (1)10uF
CVCORECapacitor connected between VCORE and VSS (1)(2)470nF
(1) Connect CVDD and CVCORE between VDD and VSS and VCORE/VSS, respectively, as close to the device pins as possible.  A low-ESR capacitor with at least the specified value and tolerance of ±20% or better is required for CVDD and CVCORE.
(2) The VCORE pin must only be connected to CVCORE.  Do not supply any voltage or apply any external load to the VCORE pin.
(3) Wait states are managed automatically by the system controller (SYSCTL) and do not need to be configured by application software unless MCLK is sourced from a high speed clock source (HSCLK sourced from HFCLK or SYSPLL)