SLAAET8A April   2025  â€“ December 2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0C1105 , MSPM0C1106 , MSPM0C1106-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0G3529-Q1 , MSPM0H3216 , MSPM0H3216-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2EMC and EMC Standards
    1. 2.1 EMC
      1. 2.1.1 EMS
      2. 2.1.2 EMI
    2. 2.2 EMC Standards
      1. 2.2.1 EMC Standards Category
    3. 2.3 EMC and IC Electrical Reliability in TI
  6. 3EMC Improvement Guidelines Summary
    1. 3.1 PCB Design Guidelines
    2. 3.2 Firmware Guidelines
  7. 4EMC Improvement Features on MSPM0
    1. 4.1 Susceptibility Protection Features
      1. 4.1.1 POR and BOR
      2. 4.1.2 NMI and Hard Fault
      3. 4.1.3 I/O ESD and Settings
    2. 4.2 Emission Reduction Features
      1. 4.2.1 Clock Source
      2. 4.2.2 Power Modes
      3. 4.2.3 Package
  8. 5Analysis for EMS Test
    1. 5.1 Root Cause Analysis
      1. 5.1.1 Permanent Damage
      2. 5.1.2 Recoverable Malfunction
    2. 5.2 Debug Flow
  9. 6Analysis for EMI Test
    1. 6.1 Root Cause Analysis
      1. 6.1.1 Power Line
      2. 6.1.2 External Vcore
    2. 6.2 Debug Flow
  10. 7Summary
  11. 8References
  12. 9Revision History

4.2.2 Power Modes

The power modes of a microcontroller (MCU) significantly influence EMI due to variations in clock and peripherals activities. In MCU operation, high-frequency clock signals generate strong harmonics. Discrete spectral peaks from synchronized clock networks (for example, CPU, peripherals) amplify radiation.

The MSPM0 series provide five main operating modes (power modes) to allow for optimization of the device power consumption based on application requirements. The modes are: RUN, SLEEP, STOP, STANDBY, and SHUTDOWN. Different power modes represent the different available clock sources and different available peripherals. In every power mode, there are three mode policy options generated by limiting the max system clock frequency. An example of the supported functionality in each operating mode is shown in Table 4-6. For the full table and workable peripherals under different conditions, refer to the device-specific MSPM0 data sheet.

Table 4-6 Supported Functionality by Operating Mode of MSPM0G
Operating ModeRunSleepStopStandby
RUN0RUN1RUN2SLEEP0SLEEP1SLEEP2STOP0STOP1STOP2STANDBY0STANDBY1
OscillatorsSYSOSCENENDISENENDISOPTENDISDISDIS
LFOSC or LFXTEN (LFOSC or LFXT)
HFXTOPTDISDISOPTDISDISDISDISDISDISDIS
SYSPLLOPTNSNSOPTNSNSNSNSNSNSNS
ClocksCPUCLK80MHz32kHz32kHzDIS
MCLK to PD1 80MHz32kHz32kHz80MHz32kHz32kHzDIS
ULPCLK to PD0 40MHz32kHz32kHz40MHz32kHz32kHz4MHz4MHz32kHzDIS
LFCLK32kHzDIS
Core functionsCPUENDIS
DMAOPTDIS (triggers supported)
FlashENDIS
SRAMENDIS

Analyze the working frequency and current consumption of digital peripherals and core function to evaluate the emission noise level. To find this information, refer to the device data sheet and the MSPM0G3507 Low Power Test and Guidance.

TI recommends to choose a valid power mode level and mode policy options for the related MCU operation requirement.