ZHCSQT5 July   2022 TPS7A57

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Soft-Start (NR/SS Pin)
      4. 7.3.4 Precision Enable and UVLO
      5. 7.3.5 Charge Pump Enable and BIAS Rail
      6. 7.3.6 Power-Good Pin (PG Pin)
      7. 7.3.7 Active Discharge
      8. 7.3.8 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Precision Enable (External UVLO)
      2. 8.1.2  Undervoltage Lockout (UVLO) Operation
        1. 8.1.2.1 IN Pin UVLO
        2. 8.1.2.2 BIAS UVLO
        3. 8.1.2.3 Typical UVLO Operation
        4. 8.1.2.4 UVLO(IN) and UVLO(BIAS) Interaction
      3. 8.1.3  Dropout Voltage (VDO)
      4. 8.1.4  Input and Output Capacitor Requirements (CIN and COUT)
      5. 8.1.5  Recommended Capacitor Types
      6. 8.1.6  Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)
      7. 8.1.7  Optimizing Noise and PSRR
      8. 8.1.8  Adjustable Operation
      9. 8.1.9  Load Transient Response
      10. 8.1.10 Current Limit and Foldback Behavior
      11. 8.1.11 Charge Pump Operation
      12. 8.1.12 Sequencing
      13. 8.1.13 Power-Good Functionality
      14. 8.1.14 Output Impedance
      15. 8.1.15 Paralleling for Higher Output Current and Lower Noise
      16. 8.1.16 Current Mode Margining
      17. 8.1.17 Voltage Mode Margining
      18. 8.1.18 Power Dissipation (PD)
      19. 8.1.19 Estimating Junction Temperature
      20. 8.1.20 TPS7A57EVM-081 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 商标
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

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8.1.6 Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)

The NR/SS pin has the dual function of controlling the soft-start time and reducing the noise generated by the internal band-gap reference and the external resistor RREF. The NR/SS capacitor (CNR/SS) reduces the output noise to very low levels and sets the output ramp rate to limit inrush current.

The device features a programmable, monotonic, voltage-controlled, soft-start circuit that is set to work with an external capacitor (CNR/SS). In addition to the soft-start feature, the CNR/SS capacitor also lowers the output voltage noise of the LDO. The soft-start feature can be used to eliminate power-up initialization problems. The controlled output voltage ramp also reduces peak inrush current during start up, minimizing start-up transients to the input power bus.

To achieve a monotonic start up, the device output voltage tracks the VNR/SS reference voltage until this reference reaches its set value (the set output voltage). The VNR/SS reference voltage is set by the RREF resistor and, during start up, the device uses a fast charging current (IFAST_SS), as shown in Figure 8-4, to charge the CNR/SS capacitor.

Note: Any leakage on the NR/SS and REF pins directly impacts the accuracy of the reference voltage.
GUID-20211109-SS0I-7HFF-H7MK-FC9NXNFCKGDJ-low.gif Figure 8-4 Simplified Soft-Start Circuit

The 200-μA (typical) INR/SS current quickly charges CNR/SS until its voltage reaches approximately 97% of the set output voltage, then the ISS current turns off, the switch between REF and NR/SS closes, and only the IREF current continues to charge CNR/SS to its set output voltage level.

Note: The discharge pulldown resistor on NR/SS (see the Section 7.2) is engaged when any of the GND referenced UVLOs have been tripped, or when any faults occur (overtemp, PORs, IREF bad, or OTP error) and the NRSS pin is above 50 mV.

The soft-start ramp time depends on the fast start-up (INR/SS) charging current, the reference current (IREF), CNR/SS capacitor value, and the targeted output voltage (VOUT(target)). Equation 3 calculates the soft-start ramp time.

Equation 3. Soft-start time (tSS) = (VOUT(target) × CNR/SS) / ( ISS)

The ISS current is provided in the Section 6.6 section and has a value of 200 μA (typical). The IREF current has a value of 50 μA (typical). The remaining 3% of the start-up time is determined by the RREF × CNR/SS time constant. Figure 8-5 shows the PG threshold at start up.

GUID-20211109-SS0I-QJFN-G84V-QQZJXMXSQT6H-low.gif Figure 8-5 PG Threshold During Start-Up

The output voltage noise can be lowered significantly by increasing the CNR/SS capacitor. The CNR/SS capacitor and RREF resistor form a low-pass filter (LPF) that filters out noise from the VREF voltage reference, thereby reducing the device noise floor. The LPF is a single-pole filter and Equation 4 calculates the LPF cutoff frequency. Increasing the CNR/SS capacitor can significantly lower output voltage noise, however, doing so lengthens start-up time. For low-noise applications, use a 4.7-μF CNR/SS for optimal noise and start-up time trade off.

Equation 4. Cutoff Frequency (fcutoff) = 1 / (2 × π × RREF × CNR/SS)
Note: Current limit can be entered during start up with a small CNR/SS and large COUT because VOUT no longer tracks the soft-start ramp.

Figure 8-6 and Figure 8-7 show the impact of the CNR/SS capacitor on the LDO output voltage noise.

GUID-20220405-SS0I-TNNB-F72S-JR1RGZ0GF1SS-low.png
CIN = 4.7 μF, COUT = 22 μF, VCP_EN = VIN, VIN = 5.3 V,
VOUT = 5 V, IOUT = 5 A
Figure 8-6 Output Voltage Noise Density vs CNR/SS With Charge Pump Enabled
GUID-20220405-SS0I-P4WG-L86N-3KJZXSTDKBBL-low.png
CIN = 4.7 μF, COUT = 22 μF, VIN = 5.3 V, VOUT = 5 V,
VBIAS = 11 V
Figure 8-7 Output Voltage Noise Density vs CNR/SS With Charge Pump Disabled