ZHCSQT5 July 2022 TPS7A57
PRODUCTION DATA
In this design example, the device is powered by a dc/dc convertor switching at 1 MHz. The load requires a 0.5-V clean rail with less than 5 μVRMS. The typical 22-μF input and output capacitors and 4.7-μF NR/SS capacitors are used to achieve a good balance between fast start-up time and excellent noise, and PSRR performance and load transient.
The output voltage is set using a 10-kΩ, thin-film resistor value calculated as described in the Section 7.3.1 section. The PG pin is not used and is thus connected to ground to help with thermals. The enable voltage is provided by a external I/O. Figure 8-41 illustrates that the device meets all design noise requirements. Figure 8-40 depicts adequate PSRR performance.
As illustrated in Figure 8-42, the load transient is adequate to the power-supply requirement.
Figure 8-39 depicts the implementation of these components.