ZHCSR22A June   2021  – September 2022 LP876242-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Digital Signal Descriptions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Internal Low Drop-Out Regulators (LDOVINT)
    6. 6.6  BUCK1, BUCK2, BUCK3, and BUCK4 Regulators
    7. 6.7  Reference Generator (REFOUT)
    8. 6.8  Monitoring Functions
    9. 6.9  Clocks, Oscillators, and DPLL
    10. 6.10 Thermal Monitoring and Shutdown
    11. 6.11 System Control Thresholds
    12. 6.12 Current Consumption
    13. 6.13 Digital Input Signal Parameters
    14. 6.14 Digital Output Signal Parameters
    15. 6.15 I/O Pullup and Pulldown Resistance
    16. 6.16 I2C Interface
    17. 6.17 Serial Peripheral Interface (SPI)
    18.     25
    19. 6.18 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage Monitor
      2. 7.3.2 Power Resources
        1. 7.3.2.1 Buck Regulators
          1. 7.3.2.1.1 BUCK Regulator Overview
          2. 7.3.2.1.2 Spread-Spectrum Mode
          3. 7.3.2.1.3 Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          4. 7.3.2.1.4 BUCK Output Voltage Setting
          5. 7.3.2.1.5 Sync Clock Functionality
        2. 7.3.2.2 Internal Low Dropout Regulator (LDOVINT)
      3. 7.3.3 Residual Voltage Checking
      4. 7.3.4 Output Voltage Monitor and PGOOD Generation
      5. 7.3.5 General-Purpose I/Os (GPIO Pins)
      6. 7.3.6 Thermal Monitoring
        1. 7.3.6.1 Thermal Warning Function
        2. 7.3.6.2 Thermal Shutdown
      7. 7.3.7 Interrupts
      8. 7.3.8 Watchdog (WD)
        1. 7.3.8.1 Watchdog Fail Counter and Status
        2. 7.3.8.2 Watchdog Start-Up and Configuration
        3. 7.3.8.3 MCU to Watchdog Synchronization
        4. 7.3.8.4 Watchdog Disable Function
        5. 7.3.8.5 Watchdog Sequence
        6. 7.3.8.6 Watchdog Trigger Mode
        7. 7.3.8.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8.       55
        9. 7.3.8.8 Watchdog Question-Answer Mode
          1. 7.3.8.8.1 Watchdog Q&A Related Definitions
          2. 7.3.8.8.2 Question Generation
          3. 7.3.8.8.3 Answer Comparison
            1. 7.3.8.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 7.3.8.8.3.2 Watchdog Sequence Events and Status Updates
            3. 7.3.8.8.3.3 Watchdog Q&A Sequence Scenarios
      9. 7.3.9 Error Signal Monitor (ESM)
        1. 7.3.9.1 ESM Error-Handling Procedure
        2. 7.3.9.2 Level Mode
        3.       66
        4. 7.3.9.3 PWM Mode
          1. 7.3.9.3.1 Good-Events and Bad-Events
          2. 7.3.9.3.2 ESM Error-Counter
            1. 7.3.9.3.2.1 ESM Start-Up in PWM Mode
          3. 7.3.9.3.3 ESM Flow Chart and Timing Diagrams in PWM Mode
          4.        72
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device State Machine
        1. 7.4.1.1 Fixed Device Power FSM
          1. 7.4.1.1.1 Register Resets and EEPROM read at INIT state
        2. 7.4.1.2 Pre-Configurable Mission States
          1. 7.4.1.2.1 PFSM Commands
            1. 7.4.1.2.1.1  REG_WRITE_IMM Command
            2. 7.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 7.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 7.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 7.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 7.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 7.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 7.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 7.4.1.2.1.9  SREG_READ_REG Command
            10. 7.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 7.4.1.2.1.11 WAIT Command
            12. 7.4.1.2.1.12 DELAY_IMM Command
            13. 7.4.1.2.1.13 DELAY_SREG Command
            14. 7.4.1.2.1.14 TRIG_SET Command
            15. 7.4.1.2.1.15 TRIG_MASK Command
            16. 7.4.1.2.1.16 END Command
          2. 7.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 7.4.1.2.3 Mission State Configuration
          4. 7.4.1.2.4 Pre-Configured Hardware Transitions
            1. 7.4.1.2.4.1 ON Requests
            2. 7.4.1.2.4.2 OFF Requests
            3. 7.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 7.4.1.2.4.4 WKUP1 and WKUP2 Functions
        3. 7.4.1.3 Error Handling Operations
          1. 7.4.1.3.1 Power Rail Output Error
          2. 7.4.1.3.2 Boot BIST Error
          3. 7.4.1.3.3 Runtime BIST Error
          4. 7.4.1.3.4 Catastrophic Error
          5. 7.4.1.3.5 Watchdog (WDOG) Error
          6. 7.4.1.3.6 Error Signal Monitor (ESM) Error
          7. 7.4.1.3.7 Warnings
        4. 7.4.1.4 Device Start-up Timing
        5. 7.4.1.5 Power Sequences
        6. 7.4.1.6 First Supply Detection
      2. 7.4.2 Multi-PMIC Synchronization
        1. 7.4.2.1 SPMI Interface System Setup
        2. 7.4.2.2 Transmission Protocol and CRC
          1. 7.4.2.2.1 Operation with Transmission Errors
          2. 7.4.2.2.2 Transmitted Information
        3. 7.4.2.3 SPMI Target Device Communication to SPMI Controller Device
          1. 7.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
        4. 7.4.2.4 SPMI-BIST Overview
          1. 7.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
          2. 7.4.2.4.2 Periodic Checking of the SPMI
          3. 7.4.2.4.3 SPMI Message Priorities
    5. 7.5 Control Interfaces
      1. 7.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 7.5.2 I2C-Compatible Interface
        1. 7.5.2.1 Data Validity
        2. 7.5.2.2 Start and Stop Conditions
        3. 7.5.2.3 Transferring Data
        4. 7.5.2.4 Auto-Increment Feature
      3. 7.5.3 Serial Peripheral Interface (SPI)
    6. 7.6 NVM Configurable Registers
      1. 7.6.1 Register Page Partitioning
      2. 7.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 7.6.3 CRC Protection for User Registers
      4. 7.6.4 Register Write Protection
        1. 7.6.4.1 ESM and Watchdog Configuration Registers
        2. 7.6.4.2 User Registers
    7. 7.7 Register Map
      1. 7.7.1 LP876242_map Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Buck Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
        4. 8.2.1.4 LDO Output Capacitor Selection
        5. 8.2.1.5 VCCA Supply Filtering Components
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Voltage Scaling Precautions
      4. 8.2.4 Application Curves
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
    4. 8.4 Power Supply Recommendations
  9. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 术语表
  10. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.8 Monitoring Functions

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics: BUCK REGULATORS OUTPUT, VMONx INPUT
5.1a VBUCK_OV_TH , VVMON_OV_TH Overvoltage monitoring for buck output and VMONx pin input, programable threshold accuracy, VOUT_Bx / VVMONx > 1 V(1) BUCKn_OV_THR / VMONn_OV_THR = 0x0, VMONn_RANGE_SEL = 0 2% 3% 4%
5.1b BUCKn_OV_THR / VMONn_OV_THR = 0x1, VMONn_RANGE_SEL = 0 2.5% 3.5% 4.5%
5.1c BUCKn_OV_THR / VMONn_OV_THR = 0x2, VMONn_RANGE_SEL = 0 3% 4% 5%
5.1d BUCKn_OV_THR / VMONn_OV_THR = 0x3, VMONn_RANGE_SEL = 0 4% 5% 6%
5.1e BUCKn_OV_THR / VMONn_OV_THR = 0x4, VMONn_RANGE_SEL = 0 5% 6% 7%
5.1f BUCKn_OV_THR / VMONn_OV_THR = 0x5, VMONn_RANGE_SEL = 0 6% 7% 8%
5.1g BUCKn_OV_THR / VMONn_OV_THR = 0x6, VMONn_RANGE_SEL = 0 7% 8% 9%
5.1h BUCKn_OV_THR / VMONn_OV_THR = 0x7, VMONn_RANGE_SEL = 0 9% 10% 11%
5.2a VBUCK_OV_TH_mv , VVMON_OV_TH_mv Overvoltage monitoring for buck output and VMONx pin input, programable threshold accuracy, VOUT_Bx / VVMONx ≤ 1 V(1) BUCKn_OV_THR / VMONn_OV_THR = 0x0, VMONn_RANGE_SEL = 0 20 30 40 mV
5.2b BUCKn_OV_THR / VMONn_OV_THR = 0x1, VMONn_RANGE_SEL = 0 25 35 45
5.2c BUCKn_OV_THR / VMONn_OV_THR = 0x2, VMONn_RANGE_SEL = 0 30 40 50
5.2d BUCKn_OV_THR / VMONn_OV_THR = 0x3, VMONn_RANGE_SEL = 0 40 50 60
5.2e BUCKn_OV_THR / VMONn_OV_THR = 0x4, VMONn_RANGE_SEL = 0 50 60 70
5.2f BUCKn_OV_THR / VMONn_OV_THR = 0x5, VMONn_RANGE_SEL = 0 60 70 80
5.2g BUCKn_OV_THR / VMONn_OV_THR = 0x6, VMONn_RANGE_SEL = 0 70 80 90
5.2h BUCKn_OV_THR / VMONn_OV_THR = 0x7, VMONn_RANGE_SEL = 0 90 100 110
5.3a VBUCK_UV_TH , VVMON_UV_TH Undervoltage monitoring for buck output and VMONx pin input, programable threshold accuracy, VOUT_Bx / VVMONx > 1 V(1) BUCKn_UV_THR / VMONn_UV_THR = 0x0, VMONn_RANGE_SEL = 0 –4% –3% –2%
5.3b BUCKn_UV_THR / VMONn_UV_THR = 0x1, VMONn_RANGE_SEL = 0 –4.5% –3.5% –2.5%
5.3c BUCKn_UV_THR / VMONn_UV_THR = 0x2, VMONn_RANGE_SEL = 0 –5% –4% –3%
5.3d BUCKn_UV_THR / VMONn_UV_THR = 0x3, VMONn_RANGE_SEL = 0 –6% –5% –4%
5.3e BUCKn_UV_THR / VMONn_UV_THR = 0x4, VMONn_RANGE_SEL = 0 –7% –6% –5%
5.3f BUCKn_UV_THR / VMONn_UV_THR = 0x5, VMONn_RANGE_SEL = 0 –8% –7% –6%
5.3g BUCKn_UV_THR / VMONn_UV_THR = 0x6, VMONn_RANGE_SEL = 0 –9% –8% –7%
5.3h BUCKn_UV_THR / VMONn_UV_THR = 0x7, VMONn_RANGE_SEL = 0 –11% –10% –9%
5.4a VBUCK_UV_TH_mv , VVMON_UV_TH_mv Undervoltage monitoring for buck output and VMONx pin input, programable threshold accuracy, VOUT_Bx / VVMONx ≤ 1 V(1) BUCKn_UV_THR / VMONn_UV_THR = 0x0, VMONn_RANGE_SEL = 0 –40 –30 –20 mV
5.4b BUCKn_UV_THR / VMONn_UV_THR = 0x1, VMONn_RANGE_SEL = 0 –45 –35 –25
5.4c BUCKn_UV_THR / VMONn_UV_THR = 0x2, VMONn_RANGE_SEL = 0 –50 –40 –30
5.4d BUCKn_UV_THR / VMONn_UV_THR = 0x3, VMONn_RANGE_SEL = 0 –60 –50 –40
5.4e BUCKn_UV_THR / VMONn_UV_THR = 0x4, VMONn_RANGE_SEL = 0 –70 –60 –50
5.4f BUCKn_UV_THR / VMONn_UV_THR = 0x5, VMONn_RANGE_SEL = 0 –80 –70 –60
5.4g BUCKn_UV_THR / VMONn_UV_THR = 0x6, VMONn_RANGE_SEL = 0 –90 –80 –70
5.4h BUCKn_UV_THR / VMONn_UV_THR = 0x7, VMONn_RANGE_SEL = 0 –110 –100 –90
5.5a VVMON_OV_TH2 Overvoltage monitoring for VMONx pin input with extended range(1) VMONn_OV_THR = 0x0, VMONn_RANGE_SEL = 1 100 150 200 mV
5.5b VMONn_OV_THR = 0x1, VMONn_RANGE_SEL = 1 125 175 225
5.5c VMONn_OV_THR = 0x2, VMONn_RANGE_SEL = 1 150 200 250
5.5d VMONn_OV_THR = 0x3, VMONn_RANGE_SEL = 1 200 250 300
5.5e VMONn_OV_THR = 0x4, VMONn_RANGE_SEL = 1 250 300 350
5.5f VMONn_OV_THR = 0x5, VMONn_RANGE_SEL = 1 300 350 400
5.5g VMONn_OV_THR = 0x6, VMONn_RANGE_SEL = 1 350 400 450
5.5h VMONn_OV_THR = 0x7, VMONn_RANGE_SEL = 1 450 500 550
5.6a VVMON_UV_TH2 Undervoltage monitoring for VMONx pin input with extended range(1) VMONn_UV_THR = 0x0, VMONn_RANGE_SEL = 1 -200 -150 -100 mV
5.6b VMONn_UV_THR = 0x1, VMONn_RANGE_SEL = 1 -225 -175 -125
5.6c VMONn_UV_THR = 0x2, VMONn_RANGE_SEL = 1 -250 -200 -150
5.6d VMONn_UV_THR = 0x3, VMONn_RANGE_SEL = 1 -300 -250 -200
5.6e VMONn_UV_THR = 0x4, VMONn_RANGE_SEL = 1 -350 -300 -250
5.6f VMONn_UV_THR = 0x5, VMONn_RANGE_SEL = 1 -400 -350 -300
5.6g VMONn_UV_THR = 0x6, VMONn_RANGE_SEL = 1 -450 -400 -350
5.6h VMONn_UV_THR = 0x7, VMONn_RANGE_SEL = 1 -550 -500 -450
5.6i VTH_RV(VMON) Threshold voltage for Residual Voltage Detection at VMONx pins 140 150 160 mV
Electrical Characteristics: VCCA INPUT
5.7a VCCAOV_TH Overvoltage monitoring for VCCA input, programable threshold accuracy(2) VCCA_OV_THR = 0x0 2% 3% 4%
5.7b VCCA_OV_THR = 0x1 2.5% 3.5% 4.5%
5.7c VCCA_OV_THR = 0x2 3% 4% 5%
5.7d VCCA_OV_THR = 0x3 4% 5% 6%
5.7e VCCA_OV_THR = 0x4 5% 6% 7%
5.7f VCCA_OV_THR = 0x5 6% 7% 8%
5.7g VCCA_OV_THR = 0x6 7% 8% 9%
5.7h VCCA_OV_THR = 0x7 9% 10% 11%
5.8a VCCAUV_TH Undervoltage monitoring for VCCA input, programable threshold accuracy(2) VCCA_UV_THR = 0x0 -4% -3% -2%
5.8b VCCA_UV_THR = 0x1 -4.5% -3.5% -2.5%
5.8c VCCA_UV_THR = 0x2 -5% -4% -3%
5.8d VCCA_UV_THR = 0x3 -6% -5% -4%
5.8e VCCA_UV_THR = 0x4 -7% -6% -5%
5.8f VCCA_UV_THR = 0x5 -8% -7% -6%
5.8g VCCA_UV_THR = 0x6 -9% -8% -7%
5.8h VCCA_UV_THR = 0x7 -11% -10% -9%
Timing Requirements
5.9a tdelay_OV_UV BUCK and VMON OV/UV detection delay Detection delay with 5mV (Vin ≤ 1 V) or 0.5% (Vin > 1 V) over/underdrive 8 µs
5.9b tdelay_VCCA_OV_UV VCCA OV/UV detection delay Detection delay with 30mV over/underdrive 8 µs
5.10a tdeglitch0_OV_UV VCCA, BUCK and VMON OV/UV signal deglitch time VMON_DEGLITCH_SEL is 0.5 µs:  Digital deglitch time for detected signal 0.5 1 µs
5.10b tdeglitch1_OV_UV VMON_DEGLITCH_SEL is 4 µs: Digital deglitch time for detected signal 3.4 3.8 4.2
5.10c tdeglitch2_OV_UV VMON_DEGLITCH_SEL is 20 µs: Digital deglitch time for detected signal 18 20 22
5.11a tlatency0_OV_UV BUCK and VMON OV/UV signal latency time VMON_DEGLITCH_SEL is 0.5 µs: Total delay from 5mV (Vin ≤ 1 V) or 0.5% (Vin > 1 V) over/underdrive to interrupt or PFSM trigger 9 µs
5.11b tlatency1_OV_UV VMON_DEGLITCH_SEL is 4 µs: Total delay from 5mV (Vin ≤ 1 V) or 0.5% (Vin > 1 V) over/underdrive to interrupt or PFSM trigger 13
5.11c tlatency2_OV_UV VMON_DEGLITCH_SEL is 20 µs: Total delay from 5mV (Vin ≤ 1 V) or 0.5% (Vin > 1 V) over/underdrive to interrupt or PFSM trigger 30
5.11d tlatency0_VCCA_OV_UV VCCA OV/UV signal latency time VMON_DEGLITCH_SEL is 0.5 µs: Total delay from 30mV over/underdrive to interrupt or PFSM trigger 9 µs
5.11e tlatency1_VCCA_OV_UV VMON_DEGLITCH_SEL is 4 µs: Total delay from 30mV over/underdrive to interrupt or PFSM trigger 13
5.11f tlatency2_VCCA_OV_UV VMON_DEGLITCH_SEL is 20 µs: Total delay from 30mV over/underdrive to interrupt or PFSM trigger 30
5.12a tdeglitch_PGOOD_rise PGOOD signal additional deglitch time Input signal transition from invalid to valid 9.5 10.5 µs
5.12b tdeglitch_PGOOD_fall Input signal transition from valid to invalid 0
(1) The default values of BUCKn_OV_THR, BUCKn_UV_THR, VMONn_OV_THR and VMONn_UV_THR registers come from the NVM memory, and can be re-programmed by software.
(2) The default values of VCCA_OV_THR and VCCA_UV_THR registers come from the NVM memory, and can be re-programmed by software.