ZHCSR22A June   2021  – September 2022 LP876242-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Digital Signal Descriptions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Internal Low Drop-Out Regulators (LDOVINT)
    6. 6.6  BUCK1, BUCK2, BUCK3, and BUCK4 Regulators
    7. 6.7  Reference Generator (REFOUT)
    8. 6.8  Monitoring Functions
    9. 6.9  Clocks, Oscillators, and DPLL
    10. 6.10 Thermal Monitoring and Shutdown
    11. 6.11 System Control Thresholds
    12. 6.12 Current Consumption
    13. 6.13 Digital Input Signal Parameters
    14. 6.14 Digital Output Signal Parameters
    15. 6.15 I/O Pullup and Pulldown Resistance
    16. 6.16 I2C Interface
    17. 6.17 Serial Peripheral Interface (SPI)
    18.     25
    19. 6.18 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage Monitor
      2. 7.3.2 Power Resources
        1. 7.3.2.1 Buck Regulators
          1. 7.3.2.1.1 BUCK Regulator Overview
          2. 7.3.2.1.2 Spread-Spectrum Mode
          3. 7.3.2.1.3 Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          4. 7.3.2.1.4 BUCK Output Voltage Setting
          5. 7.3.2.1.5 Sync Clock Functionality
        2. 7.3.2.2 Internal Low Dropout Regulator (LDOVINT)
      3. 7.3.3 Residual Voltage Checking
      4. 7.3.4 Output Voltage Monitor and PGOOD Generation
      5. 7.3.5 General-Purpose I/Os (GPIO Pins)
      6. 7.3.6 Thermal Monitoring
        1. 7.3.6.1 Thermal Warning Function
        2. 7.3.6.2 Thermal Shutdown
      7. 7.3.7 Interrupts
      8. 7.3.8 Watchdog (WD)
        1. 7.3.8.1 Watchdog Fail Counter and Status
        2. 7.3.8.2 Watchdog Start-Up and Configuration
        3. 7.3.8.3 MCU to Watchdog Synchronization
        4. 7.3.8.4 Watchdog Disable Function
        5. 7.3.8.5 Watchdog Sequence
        6. 7.3.8.6 Watchdog Trigger Mode
        7. 7.3.8.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8.       55
        9. 7.3.8.8 Watchdog Question-Answer Mode
          1. 7.3.8.8.1 Watchdog Q&A Related Definitions
          2. 7.3.8.8.2 Question Generation
          3. 7.3.8.8.3 Answer Comparison
            1. 7.3.8.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 7.3.8.8.3.2 Watchdog Sequence Events and Status Updates
            3. 7.3.8.8.3.3 Watchdog Q&A Sequence Scenarios
      9. 7.3.9 Error Signal Monitor (ESM)
        1. 7.3.9.1 ESM Error-Handling Procedure
        2. 7.3.9.2 Level Mode
        3.       66
        4. 7.3.9.3 PWM Mode
          1. 7.3.9.3.1 Good-Events and Bad-Events
          2. 7.3.9.3.2 ESM Error-Counter
            1. 7.3.9.3.2.1 ESM Start-Up in PWM Mode
          3. 7.3.9.3.3 ESM Flow Chart and Timing Diagrams in PWM Mode
          4.        72
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device State Machine
        1. 7.4.1.1 Fixed Device Power FSM
          1. 7.4.1.1.1 Register Resets and EEPROM read at INIT state
        2. 7.4.1.2 Pre-Configurable Mission States
          1. 7.4.1.2.1 PFSM Commands
            1. 7.4.1.2.1.1  REG_WRITE_IMM Command
            2. 7.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 7.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 7.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 7.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 7.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 7.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 7.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 7.4.1.2.1.9  SREG_READ_REG Command
            10. 7.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 7.4.1.2.1.11 WAIT Command
            12. 7.4.1.2.1.12 DELAY_IMM Command
            13. 7.4.1.2.1.13 DELAY_SREG Command
            14. 7.4.1.2.1.14 TRIG_SET Command
            15. 7.4.1.2.1.15 TRIG_MASK Command
            16. 7.4.1.2.1.16 END Command
          2. 7.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 7.4.1.2.3 Mission State Configuration
          4. 7.4.1.2.4 Pre-Configured Hardware Transitions
            1. 7.4.1.2.4.1 ON Requests
            2. 7.4.1.2.4.2 OFF Requests
            3. 7.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 7.4.1.2.4.4 WKUP1 and WKUP2 Functions
        3. 7.4.1.3 Error Handling Operations
          1. 7.4.1.3.1 Power Rail Output Error
          2. 7.4.1.3.2 Boot BIST Error
          3. 7.4.1.3.3 Runtime BIST Error
          4. 7.4.1.3.4 Catastrophic Error
          5. 7.4.1.3.5 Watchdog (WDOG) Error
          6. 7.4.1.3.6 Error Signal Monitor (ESM) Error
          7. 7.4.1.3.7 Warnings
        4. 7.4.1.4 Device Start-up Timing
        5. 7.4.1.5 Power Sequences
        6. 7.4.1.6 First Supply Detection
      2. 7.4.2 Multi-PMIC Synchronization
        1. 7.4.2.1 SPMI Interface System Setup
        2. 7.4.2.2 Transmission Protocol and CRC
          1. 7.4.2.2.1 Operation with Transmission Errors
          2. 7.4.2.2.2 Transmitted Information
        3. 7.4.2.3 SPMI Target Device Communication to SPMI Controller Device
          1. 7.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
        4. 7.4.2.4 SPMI-BIST Overview
          1. 7.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
          2. 7.4.2.4.2 Periodic Checking of the SPMI
          3. 7.4.2.4.3 SPMI Message Priorities
    5. 7.5 Control Interfaces
      1. 7.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 7.5.2 I2C-Compatible Interface
        1. 7.5.2.1 Data Validity
        2. 7.5.2.2 Start and Stop Conditions
        3. 7.5.2.3 Transferring Data
        4. 7.5.2.4 Auto-Increment Feature
      3. 7.5.3 Serial Peripheral Interface (SPI)
    6. 7.6 NVM Configurable Registers
      1. 7.6.1 Register Page Partitioning
      2. 7.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 7.6.3 CRC Protection for User Registers
      4. 7.6.4 Register Write Protection
        1. 7.6.4.1 ESM and Watchdog Configuration Registers
        2. 7.6.4.2 User Registers
    7. 7.7 Register Map
      1. 7.7.1 LP876242_map Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Buck Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
        4. 8.2.1.4 LDO Output Capacitor Selection
        5. 8.2.1.5 VCCA Supply Filtering Components
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Voltage Scaling Precautions
      4. 8.2.4 Application Curves
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
    4. 8.4 Power Supply Recommendations
  9. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

Figure 5-1 RQK Package 32-Pin VQFN-HR Top View
Table 5-1 Pin Functions
PIN I/O TYPE DESCRIPTION CONNECTION IF NOT USED
NO. NAME
1 GPIO1 I/O Digital Primary function: General Purpose Input/Output signal. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground, Output: Floating
O Digital Alternative programmable function: EN_DRV - Enable Drive output pin to indicate the device entering safe state (set low when ENABLE_DRV bit is '0'). Floating
O Digital Alternative programmable function: nRSTOUT_SOC - System reset or power on reset output (low = reset). Floating
O Digital Alternative programmable function: PGOOD - Programmable Power Good indication pin. Floating
I Digital Alternative programmable function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Digital Alternative programmable function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
2 GPIO2 I/O Digital Primary function: General Purpose Input/Output signal. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground, Output: Floating
I Digital Alternative programmable function: SCL_I2C2 - Serial interface clock input for I2C access. Ground
I Digital Alternative programmable function: CS_SPI - Serial interface Chip Select signal for SPI access. Ground
I Digital Alternative programmable function: TRIG_WDOG - Trigger signal for trigger mode watchdog. Ground
I Digital Alternative programmable function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Digital Alternative programmable function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
3 GPIO3 I/O Digital Primary function: General Purpose Input/Output signal. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground, Output: Floating
I/O Digital Alternative programmable function: SDA_I2C2 - Serial interface data input and output for I2C access. Ground
O Digital Alternative programmable function: SDO_SPI - Serial interface data output signal for SPI access. Floating
I Digital Alternative programmable function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Digital Alternative programmable function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
4 SCL_I2C1/SCK_SPI I Digital If SPI is not used: SCL_I2C1 - Serial interface clock input for I2C access. Ground
I Digital If SPI is used: SCK_SPI - Serial interface clock input for SPI access. Ground
5 SDA_I2C1/SDI_SPI I/O Digital If SPI is not used: SDA_I2C1 - Serial interface data input and output for I2C access. Ground
I Digital If SPI is used: SDI_SPI - Serial interface data input signal for SPI access. Ground
6 FB_B2 — Analog Output voltage feedback (positive) for BUCK2. Ground
7 FB_B1 — Analog Output voltage feedback (positive) for BUCK1. Ground
8 GPIO4 I/O Digital Primary function: General Purpose Input/Output signal. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground, Output: Floating
I Digital Alternative programmable function: ENABLE - External power-on control. Ground
I Digital Alternative programmable function: TRIG_WDOG - Trigger signal for trigger mode watchdog. Ground
— Analog Alternative programmable function: BUCK1_VMON - Voltage monitoring input for BUCK1 regulator. Ground
I Digital Alternative programmable function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Digital Alternative programmable function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
9 nINT O Digital Open-drain interrupt output, active LOW. Floating
10 GPIO5 I/O Digital Primary function: General Purpose Input/Output signal. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground, Output: Floating
I Digital Alternative programmable function: SYNCCLKIN - External switching clock input for Buck regulators. Ground
O Digital Alternative programmable function: SYNCCLKOUT - Switching clock output for external regulators. Floating
O Digital Alternative programmable function: nRSTOUT_SOC - System reset or power on reset output (low = reset). Floating
I Digital Alternative programmable function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Digital Alternative programmable function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
11 SW_B1 — Analog BUCK1 switch node. Floating
12 PVIN_B1 — Power Power input for BUCK1. The separate power pins PVIN_Bx are not connected together internally – PVIN_Bx and VCCA pins must be connected together in the application and be locally bypassed. System supply
13 PGND — Ground Power ground for Buck regulators. Ground
14 PVIN_B2 — Power Power input for BUCK2. The separate power pins PVIN_Bx are not connected together internally – PVIN_Bx and VCCA pins must be connected together in the application and be locally bypassed. System supply
15 SW_B2 — Analog BUCK2 switch node. Floating
16 GPIO6 I/O Digital Primary function: General Purpose Input/Output signal. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground, Output: Floating
I Digital Alternative programmable function: nERR_MCU - System error count down input signal from the MCU. Floating
O Digital Alternative programmable function: SYNCCLKOUT - Switching clock output for external regulators. Floating
O Digital Alternative programmable function: PGOOD - Programmable Power Good indication pin. Floating
I Digital Alternative programmable function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Digital Alternative programmable function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
17 GPIO7 I/O Digital Primary function: General Purpose Input/Output signal. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground, Output: Floating
I Digital Alternative programmable function: nERR_MCU - System error count down input signal from the MCU. Floating
O Analog Alternative programmable function: REFOUT - Buffered bandgap output. Floating
I Analog Alternative programmable function: VMON1 - External voltage monitoring input. Ground
I Digital Alternative programmable function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Digital Alternative programmable function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
18 VCCA — Power Supply voltage for internal LDO. VCCA and PVIN_Bx pins must be connected together in the application and be locally bypassed. System supply
19 AGND1 — Ground Ground Ground
20 VOUT_LDO — Power LDO regulator filter node. LDO is used for internal purposes. —
21 AGND2 — Ground Ground Ground
22 FB_B4 — Analog Output voltage feedback (positive) for BUCK4. Ground
23 FB_B3 — Analog Output voltage feedback (positive) for BUCK3. Ground
24 VIO — Power Supply voltage for selected digital outputs. Ground
25 GPIO8 I/O Digital Primary function: General Purpose Input/Output signal. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground, Output: Floating
I/O Digital Alternative programmable function: SCLK_SPMI - Multi-PMIC SPMI serial interface clock signal. This pin is an output pin for the master SPMI device, and an input pin for the slave SPMI device. Ground
I Analog Alternative programmable function: VMON2 - External voltage monitoring input. Ground
I Digital Alternative programmable function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Digital Alternative programmable function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
26 GPIO9 I/O Digital Primary function: General Purpose Input/Output signal. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground, Output: Floating
I/O Digital Alternative programmable function: SDATA_SPMI - Multi-PMIC SPMI serial interface bidirectional data signal Floating
O Digital Alternative programmable function: PGOOD - Programmable Power Good indication pin. Floating
I Digital Alternative programmable function: SYNCCLKIN - External switching clock input for Buck regulators. Ground
I Digital Alternative programmable function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Digital Alternative programmable function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
27 SW_B3 — Analog BUCK3 switch node. Floating
28 PVIN_B3 — Power Power input for BUCK3. The separate power pins PVIN_Bx are not connected together internally – PVIN_Bx and VCCA pins must be connected together in the application and be locally bypassed. System supply
30 PVIN_B4 — Power Power input for BUCK4. The separate power pins PVIN_Bx are not connected together internally – PVIN_Bx and VCCA pins must be connected together in the application and be locally bypassed. System supply
31 SW_B4 — Analog BUCK4 switch node. Floating
32 GPIO10 I/O Digital Primary function: General Purpose Input/Output signal. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground, Output: Floating
O Digital Alternative programmable function: nRSTOUT - System reset or power on reset output (low = reset). Floating
O Digital Alternative programmable function: nRSTOUT_SOC - System reset or power on reset output (low = reset). Floating
I Digital Alternative programmable function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Digital Alternative programmable function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground