SLUSFR7 August 2025 BQ24810
PRODUCTION DATA
The BQ24810 device operates as a slave, receiving control inputs from the embedded controller host through the SMBus interface. This devices uses a simplified subset of the commands documented in System Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The BQ248110 may use the SMBus read-word and write-word protocols (shown in Table 6-4 and Table 6-5) to receive commands from a smart battery. The BQ24810 device performs only as a SMBus slave device with address 0x12. Note that this SMBUS address is written in 8-bit format, which is the 7-bit SMBus address with a "0" bit appended to represent the R/W bit. The corresponding 7-bit address is 0x09. The BQ24810 does not initiate communication on the bus. The BQ24810 has two identification registers, a 16-bit device ID register (0xFF) and a 16-bit manufacturer ID register (0xFE). The BQ24810 has manufacturer ID of 0x40 and device ID of 0x08.
SMBus communication starts when VCC is above UVLO.
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose pull-up resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications. Communication starts when the master signals a start condition, which is a high-to-low transition on SDA, while SCL is high. When the master has finished communicating, the master issues a stop condition, which is a low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 6-4 and Figure 6-5 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and data bytes are transmitted between the start and stop conditions. The SDA state changes only while SCL is low, except for the start and stop conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the device because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The BQ24810 supports the charger commands listed in Table 6-4.