ZHCSRW0A February   2023  – August 2023 AM68 , AM68A

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
    1. 3.1 功能方框图
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
      2.      12
    3. 6.3 Signal Descriptions
      1.      14
      2. 6.3.1  ADC
        1. 6.3.1.1 MCU Domain
          1.        17
          2.        18
          3.        19
      3. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
          1.        22
          2.        23
      4. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
          1.        26
        2. 6.3.3.2 WKUP Domain
          1.        28
      5. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
          1.        31
          2.        32
          3.        33
          4.        34
          5.        35
          6.        36
          7.        37
        2. 6.3.4.2 MCU Domain
          1.        39
          2.        40
        3. 6.3.4.3 WKUP Domain
          1.        42
      6. 6.3.5  I3C
        1. 6.3.5.1 MCU Domain
          1.        45
      7. 6.3.6  MCAN
        1. 6.3.6.1 MAIN Domain
          1.        48
          2.        49
          3.        50
          4.        51
          5.        52
          6.        53
          7.        54
          8.        55
          9.        56
          10.        57
          11.        58
          12.        59
          13.        60
          14.        61
          15.        62
          16.        63
          17.        64
          18.        65
        2. 6.3.6.2 MCU Domain
          1.        67
          2.        68
      8. 6.3.7  MCSPI
        1. 6.3.7.1 MAIN Domain
          1.        71
          2.        72
          3.        73
          4.        74
          5.        75
          6.        76
          7.        77
        2. 6.3.7.2 MCU Domain
          1.        79
          2.        80
      9. 6.3.8  UART
        1. 6.3.8.1 MAIN Domain
          1.        83
          2.        84
          3.        85
          4.        86
          5.        87
          6.        88
          7.        89
          8.        90
          9.        91
          10.        92
        2. 6.3.8.2 MCU Domain
          1.        94
        3. 6.3.8.3 WKUP Domain
          1.        96
      10. 6.3.9  MDIO
        1. 6.3.9.1 MAIN Domain
          1.        99
        2. 6.3.9.2 MCU Domain
          1.        101
      11. 6.3.10 CPSW2G
        1. 6.3.10.1 MAIN Domain
          1.        104
        2. 6.3.10.2 MCU Domain
          1.        106
      12. 6.3.11 ECAP
        1. 6.3.11.1 MAIN Domain
          1.        109
          2.        110
          3.        111
      13. 6.3.12 EQEP
        1. 6.3.12.1 MAIN Domain
          1.        114
          2.        115
          3.        116
      14. 6.3.13 EPWM
        1. 6.3.13.1 MAIN Domain
          1.        119
          2.        120
          3.        121
          4.        122
          5.        123
          6.        124
          7.        125
      15. 6.3.14 USB
        1. 6.3.14.1 MAIN Domain
          1.        128
      16. 6.3.15 Display Port
        1. 6.3.15.1 MAIN Domain
          1.        131
      17. 6.3.16 Hyperlink
        1. 6.3.16.1 MAIN Domain
          1.        134
          2.        135
          3.        136
      18. 6.3.17 PCIE
        1. 6.3.17.1 MAIN Domain
          1.        139
      19. 6.3.18 SERDES
        1. 6.3.18.1 MAIN Domain
          1.        142
      20. 6.3.19 DSI
        1. 6.3.19.1 MAIN Domain
          1.        145
          2.        146
      21. 6.3.20 CSI
        1. 6.3.20.1 MAIN Domain
          1.        149
          2.        150
      22. 6.3.21 MCASP
        1. 6.3.21.1 MAIN Domain
          1.        153
          2.        154
          3.        155
          4.        156
          5.        157
      23. 6.3.22 DMTIMER
        1. 6.3.22.1 MAIN Domain
          1.        160
        2. 6.3.22.2 MCU Domain
          1.        162
      24. 6.3.23 CPTS
        1. 6.3.23.1 MAIN Domain
          1.        165
        2. 6.3.23.2 MCU Domain
          1.        167
      25. 6.3.24 DSS
        1. 6.3.24.1 MAIN Domain
          1.        170
      26. 6.3.25 GPMC
        1. 6.3.25.1 MAIN Domain
          1.        173
      27. 6.3.26 MMC
        1. 6.3.26.1 MAIN Domain
          1.        176
          2.        177
      28. 6.3.27 OSPI
        1. 6.3.27.1 MCU Domain
          1.        180
          2.        181
      29. 6.3.28 Hyperbus
        1. 6.3.28.1 MCU Domain
          1.        184
      30. 6.3.29 Emulation and Debug
        1. 6.3.29.1 MAIN Domain
          1.        187
          2.        188
      31. 6.3.30 System and Miscellaneous
        1. 6.3.30.1 Boot Mode configuration
          1.        191
        2. 6.3.30.2 Clock
          1.        193
          2.        194
        3. 6.3.30.3 System
          1.        196
          2.        197
        4. 6.3.30.4 EFUSE
          1.        199
        5. 6.3.30.5 VMON
          1.        201
      32. 6.3.31 Power
        1.       203
    4. 6.4 Connection for Unused Pins
  8. 7 Specifications
    1. 7.1  绝对最大额定值
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Power-On-Hour (POH) Limits
    5. 7.5  Operating Performance Points
    6. 7.6  Electrical Characteristics
      1. 7.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 7.6.3  HFOSC/LFOSC Electrical Characteristics
      4. 7.6.4  eMMCPHY Electrical Characteristics
      5. 7.6.5  SDIO Electrical Characteristics
      6. 7.6.6  CSI2/DSI D-PHY Electrical Characteristics
      7. 7.6.7  ADC12B Electrical Characteristics
      8. 7.6.8  LVCMOS Electrical Characteristics
      9. 7.6.9  USB2PHY Electrical Characteristics
      10. 7.6.10 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      11. 7.6.11 UFS M-PHY Electrical Characteristics
      12. 7.6.12 eDP/DP AUX-PHY Electrical Characteristics
      13. 7.6.13 DDR0 Electrical Characteristics
    7. 7.7  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.7.2 Hardware Requirements
      3. 7.7.3 Programming Sequence
      4. 7.7.4 Impact to Your Hardware Warranty
    8. 7.8  Thermal Resistance Characteristics
      1. 7.8.1 Thermal Resistance Characteristics for ALZ Package
    9. 7.9  Temperature Sensor Characteristics
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Sequencing
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Combined MCU and Main Domains Power- Up Sequencing
        3. 7.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 7.10.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 7.10.2.5 Isolated MCU and Main Domains Power- Down Sequencing
        6. 7.10.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        7. 7.10.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        8. 7.10.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input and Output Clocks / Oscillators
          1. 7.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 7.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 7.10.4.1.3.1 Load Capacitance
            2. 7.10.4.1.3.2 Shunt Capacitance
          4. 7.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 7.10.4.1.5 Auxiliary OSC1 Not Used
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
        4. 7.10.4.4 Module and Peripheral Clocks Frequencies
      5. 7.10.5 Peripherals
        1. 7.10.5.1  ATL
          1. 7.10.5.1.1 ATL_PCLK Timing Requirements
          2. 7.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 7.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 7.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 7.10.5.2  CPSW2G
          1. 7.10.5.2.1 CPSW2G MDIO Interface Timings
          2. 7.10.5.2.2 CPSW2G RMII Timings
            1. 7.10.5.2.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 7.10.5.2.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 7.10.5.2.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 7.10.5.2.3 CPSW2G RGMII Timings
            1. 7.10.5.2.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 7.10.5.2.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.10.5.2.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 7.10.5.2.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        3. 7.10.5.3  CSI-2
        4. 7.10.5.4  DDRSS
        5. 7.10.5.5  DSS
        6. 7.10.5.6  eCAP
          1. 7.10.5.6.1 Timing Requirements for eCAP
          2. 7.10.5.6.2 Switching Characteristics for eCAP
        7. 7.10.5.7  EPWM
          1. 7.10.5.7.1 Timing Requirements for eHRPWM
          2. 7.10.5.7.2 Switching Characteristics for eHRPWM
        8. 7.10.5.8  eQEP
          1. 7.10.5.8.1 Timing Requirements for eQEP
          2. 7.10.5.8.2 Switching Characteristics for eQEP
        9. 7.10.5.9  GPIO
          1. 7.10.5.9.1 GPIO Timing Requirements
          2. 7.10.5.9.2 GPIO Switching Characteristics
        10. 7.10.5.10 GPMC
          1. 7.10.5.10.1 GPMC and NOR Flash — Synchronous Mode
            1. 7.10.5.10.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 7.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 7.10.5.10.2 GPMC and NOR Flash — Asynchronous Mode
            1. 7.10.5.10.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.10.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 7.10.5.10.3 GPMC and NAND Flash — Asynchronous Mode
            1. 7.10.5.10.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.10.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 7.10.5.10.4 GPMC0 IOSET
        11. 7.10.5.11 HyperBus
          1. 7.10.5.11.1 Timing Requirements for HyperBus
          2. 7.10.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 7.10.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 7.10.5.12 I2C
        13. 7.10.5.13 I3C
        14. 7.10.5.14 MCAN
        15. 7.10.5.15 MCASP
        16. 7.10.5.16 MCSPI
          1. 7.10.5.16.1 MCSPI — Controller Mode
          2. 7.10.5.16.2 MCSPI — Peripheral Mode
        17. 7.10.5.17 MMCSD
          1. 7.10.5.17.1 MMC0 - eMMC Interface
            1. 7.10.5.17.1.1 Legacy SDR Mode
            2. 7.10.5.17.1.2 High Speed SDR Mode
            3. 7.10.5.17.1.3 High Speed DDR Mode
            4. 7.10.5.17.1.4 HS200 Mode
            5. 7.10.5.17.1.5 HS400 Mode
          2. 7.10.5.17.2 MMC1/2 - SD/SDIO Interface
            1. 7.10.5.17.2.1 Default Speed Mode
            2. 7.10.5.17.2.2 High Speed Mode
            3. 7.10.5.17.2.3 UHS–I SDR12 Mode
            4. 7.10.5.17.2.4 UHS–I SDR25 Mode
            5. 7.10.5.17.2.5 UHS–I SDR50 Mode
            6. 7.10.5.17.2.6 UHS–I DDR50 Mode
            7. 7.10.5.17.2.7 UHS–I SDR104 Mode
        18. 7.10.5.18 CPTS
          1. 7.10.5.18.1 CPTS Timing Requirements
          2. 7.10.5.18.2 CPTS Switching Characteristics
        19. 7.10.5.19 OSPI
          1. 7.10.5.19.1 OSPI0 PHY Mode
            1. 7.10.5.19.1.1 OSPI With Data Training
              1. 7.10.5.19.1.1.1 OSPI Switching Characteristics – Data Training
            2. 7.10.5.19.1.2 OSPI Without Data Training
              1. 7.10.5.19.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 7.10.5.19.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 7.10.5.19.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 7.10.5.19.1.2.4 OSPI Switching Characteristics – DDR Mode
          2. 7.10.5.19.2 OSPI0 Tap Mode
            1. 7.10.5.19.2.1 OSPI0 Tap SDR Timing
            2. 7.10.5.19.2.2 OSPI0 Tap DDR Timing
        20. 7.10.5.20 PCIE
        21. 7.10.5.21 Timers
          1. 7.10.5.21.1 Timing Requirements for Timers
          2. 7.10.5.21.2 Switching Characteristics for Timers
        22. 7.10.5.22 UART
          1. 7.10.5.22.1 Timing Requirements for UART
          2. 7.10.5.22.2 UART Switching Characteristics
        23. 7.10.5.23 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
          1. 7.10.6.2.1 JTAG Electrical Data and Timing
            1. 7.10.6.2.1.1 JTAG Timing Requirements
            2. 7.10.6.2.1.2 JTAG Switching Characteristics
  9. 8 Detailed Description
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Device Connection and Layout Fundamentals
      1. 9.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.1.1.1 Power Distribution Network Implementation Guidance
      2. 9.1.2 External Oscillator
      3. 9.1.3 JTAG and EMU
      4. 9.1.4 Reset
      5. 9.1.5 Unused Pins
      6. 9.1.6 Hardware Design Guide for JacintoTM 7 Devices
    2. 9.2 Peripheral- and Interface-Specific Design Information
      1. 9.2.1 LPDDR4 Board Design and Layout Guidelines
      2. 9.2.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.2.2.1 No Loopback and Internal Pad Loopback
        2. 9.2.2.2 External Board Loopback
        3. 9.2.2.3 DQS (only available in Octal Flash devices)
      3. 9.2.3 USB VBUS Design Guidelines
      4. 9.2.4 System Power Supply Monitor Design Guidelines using VMON/POK
      5. 9.2.5 High Speed Differential Signal Routing Guidance
      6. 9.2.6 Thermal Solution Guidance
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 工具与软件
    3. 10.3 Documentation Support
    4. 10.4 Trademarks
    5. 10.5 支持资源
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ALZ|770
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode

NO.(2)PARAMETERDESCRIPTIONMODE(19)MINMAXMINMAXUNIT
100 MHz(23)133 MHz(23)
F0tc(clk)Period, output clock GPMC_CLK(18)div_by_1_mode;
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		107.52ns
F1tw(clkH)Typical pulse duration, output clock GPMC_CLK highdiv_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 0.475*P(15)- 0.3 0.475*P(15)- 0.3ns
F1tw(clkL)Typical pulse duration, output clock GPMC_CLK lowdiv_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 0.475*P(15)- 0.3 0.475*P(15)- 0.3ns
F2td(clkH-csnV)Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] transition(14)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
no extra_delay		F(6)- 2.2F+3.75F(6)- 2.2F(6)+ 3.75ns
F3td(clkH-CSn[i]V)Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] invalid(14)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
no extra_delay		E(5)- 2.2E(5)+ 3.75E(5)- 2.2E(5)+ 3.75ns
F4td(aV-clk)Delay time, output address GPMC_A[27:1] valid to output clock GPMC_CLK first edgediv_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		B(2)-2.3B(2)+4.5B(2)-2.3B(2)+4.5ns
F5td(clkH-aIV)Delay time, output clock GPMC_CLK rising edge to output address GPMC_A[27:1] invaliddiv_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		–2.34.5–2.34.5ns
F6td(be[x]nV-clk)Delay time, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n valid to output clock GPMC_CLK first edgediv_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		B(2)-2.3B(2)+1.9B(2)-2.3B(2)+1.9ns
F7td(clkH-be[x]nIV)Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n invalid(11)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		D(4)-2.3D(4)+1.9D(4)-2.3D(4)+1.9ns
F7td(clkL-be[x]nIV)Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(12)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		D(4)-2.3D(4)+1.9D(4)-2.3D(4)+1.9ns
F7td(clkL-be[x]nIV).Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(13)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		D(4)-2.3D(4)+1.9D(4)-2.3D(4)+1.9ns
F8td(clkH-advn)Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE transitiondiv_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
no extra_delay		G(7)-2.3G(7)+4.5G(7)-2.3G(7)+4.5ns
F9td(clkH-advnIV)Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE invaliddiv_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
no extra_delay		D(4)-2.3D(4)+4.5D(4)-2.3D(4)+4.5ns
F10td(clkH-oen)Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn transitiondiv_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
no extra_delay		H(8)-2.3H(8)+3.5H(8)-2.3H(8)+3.5ns
F11td(clkH-oenIV)Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn invaliddiv_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
no extra_delay		E(8)-2.3E(8)+3.5E(8)-2.3E(8)+ 3.5ns
F14td(clkH-wen)Delay time, output clock GPMC_CLK rising edge to output write enable GPMC_WEn transitiondiv_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
no extra_delay		I(9)- 2.3I(9)+4.5I(9)- 2.3I(9)+4.5ns
F15td(clkH-do)Delay time, output clock GPMC_CLK rising edge to output data GPMC_AD[15:0] transition(11)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		J(10)-2.3J(10)+2.7J(10)-2.3J(10)+2.7ns
F15td(clkL-do)Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(12)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		J(10)-2.3J(10)+2.7J(10)-2.3J(10)+2.7ns
F15td(clkL-do).Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(13)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		J(10)-2.3J(10)+2.7J(10)-2.3J(10)+2.7ns
F17td(clkH-be[x]n)Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE transition(11)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		J(10)-2.3J(10)+1.9J(10)-2.3J(10)+1.9ns
F17td(clkL-be[x]n)Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(12)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		J(10)-2.3J(10)+1.9J(10)-2.3J(10)+1.9ns
F17td(clkL-be[x]n).Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(13)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		J(10)-2.3J(10)+1.9J(10)-2.3J(10)+1.9ns
F18tw(csnV)Pulse duration, output chip select GPMC_CSn[i] low(14)ReadA(1)A(1)ns
WriteA(1)A(1)ns
F19tw(be[x]nV)Pulse duration, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n lowReadC(3)C(3)ns
WriteC(3)C(3)ns
F20tw(advnV)Pulse duration, output address valid and address latch enable GPMC_ADVn_ALE lowReadK(16)K(16)ns
WriteK(16)K(16)ns
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
With n being the page burst access number.
(2) B = ClkActivationTime × GPMC_FCLK(17)
(3) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
With n being the page burst access number.
(4) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(5) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(6) For csn falling edge (CS activated):
  • Case GPMCFCLKDIVIDER = 0:
    • F = 0.5 × CSExtraDelay × GPMC_FCLK(17)
  • Case GPMCFCLKDIVIDER = 1:
    • F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
    • F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime) is a multiple of 3)
    • F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
    • F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
(7) For ADV falling edge (ADV activated):
  • Case GPMCFCLKDIVIDER = 0:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
  • Case GPMCFCLKDIVIDER = 1:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
    • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Reading mode:
  • Case GPMCFCLKDIVIDER = 0:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
  • Case GPMCFCLKDIVIDER = 1:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
    • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Writing mode:
  • Case GPMCFCLKDIVIDER = 0:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
  • Case GPMCFCLKDIVIDER = 1:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
    • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
(8) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
  • Case GPMCFCLKDIVIDER = 0:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
  • Case GPMCFCLKDIVIDER = 1:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime) is a multiple of 3)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
    • H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)

For OE rising edge (OE deactivated):
  • Case GPMCFCLKDIVIDER = 0:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
  • Case GPMCFCLKDIVIDER = 1:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime) is a multiple of 3)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
    • H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
(9) For WE falling edge (WE activated):
  • Case GPMCFCLKDIVIDER = 0:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(17)
  • Case GPMCFCLKDIVIDER = 1:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime) is a multiple of 3)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
    • I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)

For WE rising edge (WE deactivated):
  • Case GPMCFCLKDIVIDER = 0:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK (17)
  • Case GPMCFCLKDIVIDER = 1:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime) is a multiple of 3)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
    • I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
(10) J = GPMC_FCLK(17)
(11) First transfer only for CLK DIV 1 mode.
(12) Half cycle; for all data after initial transfer for CLK DIV 1 mode.
(13) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.
(14) In GPMC_CSn[i], i is equal to 0, 1, 2, or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
(15) P = GPMC_CLK period in ns
(16) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(17) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(18) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.
(19) For div_by_1_mode:
  • GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:
    • GPMC_CLK frequency = GPMC_FCLK frequency

  • CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100 MHz

  • GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)

For no extra_delay:
  • GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed
  • GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed
  • GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed
  • GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed
(23) For 100 MHz:
  • CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = MAIN_PLL2_HSDIV1_CLKOUT / 3
For 133 MHz:
  • CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT
GUID-A745ACF0-7F39-4057-9199-76CCB60E990F-low.gif
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 7-51 GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)
GUID-887FA4B4-AB1B-4026-BBF7-AAFDEC193153-low.gif
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 7-52 GPMC and NOR Flash — Synchronous Burst Read — 4x16–bit (GPMCFCLKDIVIDER = 0)
GUID-351B1C0C-B533-4B56-9DD3-AF952B61528F-low.gif
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 7-53 GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
GUID-4F2BF85F-133F-4547-9965-B288E9DF6FBA-low.gif
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 7-54 GPMC and Multiplexed NOR Flash — Synchronous Burst Read
GUID-C641656A-727B-43E6-AE3D-870433339E51-low.gif
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 7-55 GPMC and Multiplexed NOR Flash — Synchronous Burst Write