The following are guidelines to achieve desired controller performance relative to internal PLLs:

The DLPC900 contains four PLLs (PLLM1, PLLM2, PLLD, and PLLS), each of which have a dedicated 1.15 V digital supply; three of these PLLs (PLLM1, PLLM2, and PLLD) have a dedicated 1.8 V analog supply. It is important to have filtering on the supply pins that covers a broad frequency range. Each 1.15 V PLL supply pin must have individual high frequency filtering in the form of a ferrite bead and a 0.1 µF ceramic capacitor. These components must be located very close to the individual PLL supply balls. The impedance of the ferrite bead should far exceed that of the capacitor at frequencies above 10 MHz. The 1.15 V to the PLL supply pins must also have low frequency filtering in the form of an RC filter. This filter can be common to all the PLLs. The voltage drop across the resistor is limited by the 1.15 V regulator tolerance and the DLPC900 voltage tolerance. A resistance of 0.36 Ω and a 100 µF ceramic are recommended. Figure 9-1 shows the recommended filter topology.

Figure 9-1 Recommended Filter Topology for PLL 1.15-V Supplies

The analog 1.8-V PLL power pins must have a similar filter topology as the 1.15-V. In addition, it is recommended that a dedicated linear regulator generates the 1.8-V. Figure 9-2 shows the recommended filtering topology.

Figure 9-2 Recommended Filter Topology for PLL 1.8-V Supplies

When designing the overall supply filter network, care must be taken to ensure no resonance occurs. Specific care is required around the 1- to 2-MHz band, as this coincides with the PLL natural loop frequency.

Figure 9-3 High Frequency Decoupling

High-frequency decoupling is required for 1.15-V and 1.8-V PLL supplies and must be provided as close as possible to each of the PLL supply package pins as shown in Figure 9-3. Placing decoupling capacitors under the package on the opposite side of the board is recommended. High-quality, low-ESR, monolithic, surface-mount capacitors are recommended for use. Typically, 0.1 µF for each PLL supply should be sufficient. The length of a connecting trace increases the parasitic inductance of the mounting, and thus, where possible, there can be no trace, allowing the via to butt up against the land. Additionally, the connecting trace must be made as wide as possible. Further improvement can be made by placing vias to the side of the capacitor lands or doubling the number of vias.

The location of bulk decoupling depends on the system design.