11 Revision History
Changes from Revision F (June 2021) to Revision G (November 2023)
- 重新排列了列表并向支持的器件列表中添加了 DLP5500 DMDGo
- 编辑了高速图形速率的措辞,并添加了有关 DLP500YX 的澄清信息Go
- 移除了闪存存储器可保存的图形数量Go
- 将“视频模式”部分中的 SVGA 更正为 XGAGo
- 在 DLPC900 控制器支持的器件列表中添加了 DLP5500 DMDGo
- 删除了指向 TI.com 上不再显示的页面的链接Go
- 从#GUID-C35E90CC-29C8-4C72-96EB-B606BFE9E169/GUID-9D7DA0C9-F3AC-4E67-9EF9-A68D32A5F3B8 中删除了风扇块Go
- 枚举了可用于 DLP5500 和所有其他 DMD 的 1 位图形数量Go
- Moved placement of footnote 3 in
the
Trigger
Control Pin Function table Go
- Moved
pins
H23 and G23
from
the
Reserved Pin Functions
table
to Port1 and Port2 Channel Data and Control Pin Functions
table.Go
- Moved pins E8, B4, C4, E7, D5, E6, D3, C2, A4, B5, C6, A5, and D7
from Reserved Pin Functions table to Board-Level Test and Debug Pin Functions
tableGo
- Moved pins AD8, AE8, AF9, G24, D26, F23, F22, E24, and D25 from the
Reserved Pin Functions table to the Peripheral Interface Pin Functions
tableGo
- Removed extraneous YCbCr referenceGo
- Added
the
tSB
parameter to Table 5-1 tableGo
- Removed tEW from Table 5-1 table - duplicates tPH
Go
- Added DLPA200 to Figure 5-3
Go
- PWRGOOD cannot be uses as an early warning signal for an anticipated
power down.Go
- Changed
Power
Mode = 1
"Standby"
instructions for anticipated power
down.Go
- Changed Anticipated Power Down Sequence and Unanticipated Power Down
Sequence diagrams to match the behavior of the DLPC900
controller.Go
- Added DLP5500 DMD to list of
supported devicesGo
- Added XGA resolution to single
DLPC900 controller systems for the
DLP5500Go
- Changed phrasing from 'normal' to 'default'Go
- Changed
the
section
name from DLPC900 Memory Space to DLPC900 External Memory
SpaceGo
- Updated GPIO
signal namesGo
- Updated GPIO signal namesGo
- Removed lists of flash memory components and
added links to the appropriate BOMs on TI.com Go
- Added information about the number of 1-bit patterns the DLP5500 can
pre-load
and corrected the 1-bit depth of the DLP670S
DMDGo
- Added information to the tables about minimum exposure times for the
DLP5500Go
- Added table listing the number of 1-bit
prestored
patterns for each DMDGo
- Updated Section to include DLP5500
DMD and
reordered the DMD names.Go
- Updated block diagram and added Table 7-1
Go
- Updated DMD interface lists to
include support for the DLP5500Go
- Corrected P1_ bits to [0:9]Go
- Added information about optional GPIOs for extended external memory
accessGo
- Updated
the
schematic
to reflect the DLP5500Go
- Updated Related Documents
Table
(added
DLPLCR55EVM)Go
Changes from Revision E (March 2020) to Revision F ( June 2021)
- 更新了整个文档中的表格、图和交叉参考的编号格式Go
- Updated terminology to primary and secondary.Go
- Updated "DLP LightCrafter 9000 EVM" to "DLP LightCrafter Dual
DLPC900 Evaluation Module (EVM)"Go
- Added 10 kΩ pulldown resistor requirement to the FAULT-STATUS pin
description.Go
- Updated H22, T22, and U23 to be Flash Address line
extensionsGo
- Updated terminology to primary and secondaryGo
- DLPC900A ESD Human body model (HBM) and Charged device model (CDM)
information added.Go
- Updated terminology to primary and secondary.Go
- Updated section to include
DLP500YX and DLP670S DMDs.Go
- Updated terminology to primary and secondary.Go
- Included DLP500YX and DLP670S DMDs
in sectionGo
- Modified section to update DLPC900 Memory Space diagram and add
new information about design and layout for larger flash devices up to
128-Megabytes.Go
- Edited information regarding the amount of memory the DLPC900
can accessGo
- Updated Section 7.3.5.5.2.2 to "Combining Three Chip Selects with
One 128-Megabyte Flash" Go
- Changed "LightCrafter 6500 and the
LightCrafter 9000" to "Single DLPC900 Evaluation
Module" and "Dual DLPC900 Evaluation
Module".Go
- Added 2-Gigabit Flash Memory device to
Micron and Spansion devices listGo
- Updated link to DLP® LightCrafter™ Single DLPC900 Evaluation
Module (EVM) User's Guide (DLPU101) or DLP® LightCrafter™ Dual DLPC900 Evaluation Module
(EVM) User's Guide (DLPU102)Go
- Updated Minimum Exposure in Any Pattern Mode table to include
DLP500YX and DLP670S DMDsGo
- Updated Minimum Exposures for Number of Active DMD Blocks table to
include DLP500YX and DLP670S DMDsGo
- Updated Section to include DLP500YX and DLP670S
DMDs.Go
- Updated terminology to primary and secondary. Go
- Updated section to include DLP500YX and DLP670S DMDs. Go
- Updated Boot Flash Memory Layout to reflect updated flash
design.Go
- Updated terminology to primary and secondaryGo
- Updated Related Documents TableGo