AM62A7
Processor Cores:
- Up
to Quad 64-bit Arm
Cortex-A53 microprocessor
subsystem at up to 1.4GHz
- Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
- Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
- Single-core Arm
Cortex-R5F at up to 800MHz,
integrated as part of MCU Channel with FFI
- 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
- 512KB SRAM with SECDED ECC
- Single-core Arm
Cortex-R5F at up to 800MHz,
integrated to support Device Management
- 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
- Neural
Processing Unit based on Single-core C7™ DSP
- Floating point, 256-bit Vector C7™ DSP, up to 40 GFLOPS at 1.0GHz
- Matrix Multiply Accelerator (MMA), up to 2TOPS (8b) at 1.0GHz
- 64KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
- 1.25MB of L2 SRAM with SECDED ECC
- Vision Processing
Accelerators (VPAC) with Image Signal Processor (ISP) and
multiple vision assist accelerators:
- 315MPixel/s ISP; Up to 5MP @ 60fps
- Support for 12-bit RGB-IR
- Support for up to 16-bit input RAW format
- Line support up to 4096
- Wide Dynamic Range (WDR), Lens Distortion
Correction (LDC), Vision Imaging Subsystem (VISS),
and Multi-Scalar (MSC) support
- Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL
Multimedia:
- Display
subsystem
- Single display support
- Up to 1920x1080 @ 60fps
- Up to 165 MHz pixel clock support with independent PLL
- DPI 24-bit RGB parallel interface
- Supports safety features such as freeze frame detection and MISR data check
- One Camera Serial interface
(CSI-2) Receiver with 4-Lane D-PHY
- MIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
- Support for 1,2,3 or 4 data lane mode up to 2.5Gbps per lane
- ECC verification/correction with CRC check + ECC on RAM
- Virtual Channel support (up to 16)
- Ability to write stream data directly to DDR via DMA
- Video
Encoder/Decoder
- Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
- Support for H.264 BaseLine/Main/High Profiles at Level 5.2
- Support for up to 4K UHD resolution (3840 × 2160)
- Clocking options supporting 240MPixels/s, 120MPixels/s, or 60MPixels/s
- Motion JPEG encode at 416MPixels/s withresolutions up to 4K UHD (3840 × 2160)
Memory Subsystem:
- Up to 2.29MB of
On-chip RAM
- 64KB of On-Chip RAM (OCRAM) with SECDED ECC, can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
- 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
- 176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
- 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
- 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
- 1.25MB of L2 SRAM with SECDED ECC in Neural Processing Unit
- DDR Subsystem
(DDRSS)
- Supports LPDDR4
- 32-bit data bus with inline ECC
- Supports speeds up to 3733MT/s
- Max addressable range of 8GBytes
Functional Safety:
-
Functional Safety-Compliant
targeted [Automotive]
- Developed for functional safety applications
- Documentation will be available to aid ISO 26262 functional safety system design
- Systematic capability up to ASIL D targeted
- Hardware integrity up to ASIL B targeted
- Safety-related certification
- ISO 26262 by TÜV SÜD planned
- AEC - Q100 qualified [Automotive]
Security:
- Secure boot
supported
- Hardware-enforced Root-of-Trust (RoT)
- Support to switch RoT via backup key
- Support for takeover protection, IP protection, and anti-roll back protection
- Trusted Execution
Environment (TEE) supported
- Arm TrustZone based TEE
- Extensive firewall support for isolation
- Secure watchdog/timer/IPC
- Secure storage support
- Replay Protected Memory Block (RPMB) support
- Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
- Cryptographic
acceleration supported
- Session-aware cryptographic engine with ability
to auto-switch key-material based on incoming data
stream
- Supports cryptographic cores
- AES – 128-/192-/256-Bit key sizes
- SHA2 – 224-/256-/384-/512-Bit key sizes
- DRBG with true random number generator
- PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
- Session-aware cryptographic engine with ability
to auto-switch key-material based on incoming data
stream
- Debugging
security
- Secure software controlled debug access
- Security aware debugging
High-Speed Interfaces:
- Integrated
Ethernet switch supporting (total 2 external ports)
- RMII(10/100) or RGMII (10/100/1000)
- IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
- Clause 45 MDIO PHY management
- Packet Classifier based on ALE engine with 512 classifiers
- Priority based flow control
- Time Sensitive Networking (TSN) support
- Four CPU H/W interrupt Pacing
- IP/UDP/TCP checksum offload in hardware
- Two USB2.0
Ports
- Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
- Integrated USB VBUS detection
General Connectivity:
- 9x Universal Asynchronous Receiver-Transmitters (UART)
- 5x Serial Peripheral Interface (SPI) controllers
- 6x Inter-Integrated Circuit (I2C) ports
- 3x Multichannel
Audio Serial Ports (McASP)
- Transmit and Receive Clocks up to 50MHz
- Up to 4/6/16 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
- Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
- Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
- FIFO Buffers for Transmit and Receive (256 Bytes)
- Support for audio reference output clock
- 3x enhanced PWM modules (ePWM)
- 3x enhanced Quadrature Encoder Pulse modules (eQEP)
- 3x enhanced Capture modules (eCAP)
- General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
- 3x Controller
Area Network (CAN) modules with CAN-FD support
- Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
- Full CAN FD support (up to 64 data bytes)
- Parity/ECC check for Message RAM
- Speed up to 8Mbps
Media and Data Storage:
- 3x Multi-Media
Card/Secure
Digital (MMC/SD/SDIO) interface
- 1x 8-bit eMMC interface up to HS200 speed
- 2x 4-bit SD/SDIO interface up to UHS-I
- Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
- 1×
General-Purpose Memory Controller (GPMC) up to 133MHz
- Flexible 8- and 16-bit Asynchronous Memory Interface with up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
- Uses BCH code to support 4-, 8-, or 16-bit ECC
- Uses Hamming code to support 1-bit ECC
- Error Locator Module (ELM)
- Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
- Supports 4-, 8-, and 16-bit per 512-Byte block error location based on BCH algorithms
- OSPI/QSPI with
DDR / SDR support
- Support for Serial NAND and Serial NOR Flash devices
- 4GBytes memory address support
- XIP mode with optional on-the-fly encryption
Power Management:
- Low-power modes
supported by Device/Power Manager
- Partial IO support for CAN/GPIO/UART wakeup
- DeepSleep : I/O + DDR (suspend to RAM)
- DeepSleep
- MCU Only
- Standby
- Dynamic frequency scaling for Cortex-A53
Boot Options:
- UART
- I2C EEPROM
- OSPI/QSPI Flash
- GPMC NOR/NAND Flash
- Serial NAND Flash
- SD Card
- eMMC
- USB (host) boot from Mass Storage device
- USB (device) boot from external host (DFU mode)
- Ethernet
Technology / Package:
- 16-nm FinFET technology
- 18mm x 18mm, 0.8mm pitch full-array, 484-pin FCBGA (AMB)
- 18mm x 18mm, 0.8mm pitch full-array, 484-pin FCCSP (ANF)
AM62Ax is an extension of the Sitara™ automotive-grade family of heterogeneous Arm® processors with embedded Deep Learning (DL), Video and Vision Processing acceleration, display interface and extensive automotive peripheral and networking options. AM62Ax is built for a set of cost-sensitive automotive applications including driver and in-cabin monitoring systems, next generation of eMirror system, as well as a broad set of industrial applications in Factory Automation, Building Automation, Robotics, and other markets. The cost optimized AM62Ax provides high-performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in stand-alone Electronic Control Units (ECUs).
AM62Ax contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL) and video accelerators, a Cortex®-R5F MCU Channel core and a Cortex®-R5F Device Management core. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based-algorithms such as driver monitoring. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include the next generation C7000™ DSP from Texas Instruments (C7™ DSP) with scalar and vector cores, dedicated “MMA” deep learning accelerator enabling performance up to 2 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.
The 3-port Gigabit Ethernet switch has one internal port and two external ports with TSN support and can be used to enable industrial networking options. In addition, an extensive peripherals set is included in AM62Ax to enable system level connectivity such as USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. AM62Ax supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and also employs advanced power management support for portable and power-sensitive applications.
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The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)
WHIS-3P-SAFERTOS — WITTENSTEIN SafeRTOS 预先认证的安全 RTOS
SAFERTOS® 是专为嵌入式处理器设计的独特实时操作系统。它通过了 TÜV SÜD 的 IEC 61508 SIL3 和 ISO 26262 ASILD 标准的预先认证。SAFERTOS® 是由 WHIS 的专家团队专为安全而设计的，并在全球范围内用于安全关键型应用。WHIS 和德州仪器 (TI) 合作已有十多年。在此期间，WHIS 已将 SAFERTOS® 移植到各种 TI 处理器中，支持所有常用内核，并可按需提供其他架构。SAFERTOS® 针对您的特定处理器/编译器组合进行定制，并随附完整的源代码和设计保证包，在整个设计生命周期中提供完全透明度。许多 WHIS 客户使用 (...)
EB-3P-TRESOS — Elektrobit EB tresos Classic AUTOSAR 软件
凭借在基础软件领域数十年的经验，Elektrobit 的 EB tresos 产品系列和定制的 Classic AUTOSAR 解决方案可帮助满足各个汽车制造商的特定要求，为他们提供先进的软件。对于每个工程，Elektrobit 都能提供合适的解决方案来满足汽车 AUTOSAR 需求，从符合 OSEK-/VDX 标准的基础软件到基于 Classic AUTOSAR 的多核和功能安全系统，不一而足。
DDR-MARGIN-FW — Firmware and scripts to measure system DDR margin
USIT-3P-SECIC-HSM — Uni-Sentry SecIC-HSM 固件
SecIC-HSM 旨在满足 MCU/SoC 芯片所需的网络安全要求。HSM 固件可应用于汽车、新能源、光伏、机器人、医疗保健和航空等领域。提供的网络安全功能包括安全启动、安全通信 (SecOC)、安全诊断、安全存储、安全更新、安全调试和密钥管理。SecIC-HSM 的优点：一站式网络安全解决方案，兼容多个芯片系列，具备行业领先的性能，已在近 30 家 OEM 的量产车型中成功部署，累计部署量超过 300 万台。
USIT-3P-SECIC-PQC — Uni-Sentry SecIC-PQC 算法固件
Uni-Sentry 的安全解决方案采用 PQC 算法，能够抵御量子计算机对传统加密算法构成的解密威胁。PQC 固件与硬件安全模块 (HSM) 进行了协同优化，利用硬件加速和安全增强功能来提高加密算法执行效率和安全性。
Uni-Sentry 可持续监控全球量子计算的发展情并更新其算法组合。当前的 PQC 产品功能包括：
- SP 800-208：LMS 和 XMSS
- FIPS 203 (ML-KEM)： CRYSTALS-KYBER
- FIPS 204 (ML-DSA)： CRYSTALS-Dilithium
- FIPS 205 (SLH-DSA)：SPHINCS+
技术亮点
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ICOMMS-SWS — CouthIT 工业通信软件工程服务
CouthIT 的 Embedded Software Group 专门开发用于 TI Sitara 和 Jacinto 微处理器和微控制器的高性能工业通信软件。
凭借硬件加速的 TI 工业通信子系统 (TI ICSS) 和 TI 通用平台以太网交换机 (TI CPSW)，CouthIT 提供了领先工业通信协议的优化、可立即用于生产环境的实现方案。
该公司还提供定制和集成服务，以满足独特的应用要求，帮助客户加快产品开发，同时确保强大可靠的通信性能。
VCTR-3P-MICROSAR — 适用于微控制器和高性能计算机 (HPC) 的 Vector MICROSAR AUTOSAR 软件
MICROSAR 和 DaVinci 产品系列凭借适用于微控制器和 HPC 的先进嵌入式软件和强大的开发工具简化了 ECU 开发。利用先进的基础设施软件，即可为 ECU 奠定良好基础，并使用相关工具简化所有配套开发任务。MICROSAR 嵌入式软件是按照 AUTOSAR classic 和 adaptive 等相关标准开发的。根据 ISO 26262 高达 ASIL D 的安全标准，该软件还适用于安全相关应用。此外，智能网络安全功能可保护控制单元免受未经授权的访问和操纵。Vector 涵盖汽车和其他工业应用的所有用例。对于具有高性能计算机的软件定义车辆 (...)
VLAB-3P-V-EVM — ASTC VLAB 虚拟开发平台和工具
VLAB Works 是嵌入式电子系统建模、仿真和虚拟原型设计软件技术的行业领导者。VLAB 技术和解决方案支持将自动化和敏捷流程应用于嵌入式系统开发。VLAB Works 帮助客户设计更好的产品，提高开发效率，减少对制造和硬件的需求，并帮助构建更加环保的世界。现已推出适用于各种 TI SoC 的 VLAB 仿真功能，并可根据客户需求提供其他模型。TI SoC 仿真平台已通过 TI.com 上相关 Processor SDK 进行验证。
AM62A-PET-CALC — AM62A 功耗估算工具
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| FCBGA (AMB) | 484 | Ultra Librarian |
| FCCSP (ANF) | 484 | Ultra Librarian |
订购和质量
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