SPRUGR9H November   2010  – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678

 

  1.   Preface
    1.     About This Manual
    2.     Trademarks
    3.     Notational Conventions
    4.     Related Documentation from Texas Instruments
  2. 1Introduction
    1. 1.1  Terminology Used in This Document
    2. 1.2  KeyStone I Features
    3. 1.3  KeyStone I Functional Block Diagram
    4. 1.4  KeyStone II Changes to QMSS
    5. 1.5  KeyStone II QMSS Modes of Use
      1. 1.5.1 Shared Mode
      2. 1.5.2 Split Mode
    6. 1.6  Overview
    7. 1.7  Queue Manager
    8. 1.8  Packet DMA (PKTDMA)
    9. 1.9  Navigator Cloud
    10. 1.10 Virtualization
    11. 1.11 ARM-DSP Shared Use
    12. 1.12 PDSP Firmware
  3. 2Operational Concepts
    1. 2.1 Packets
    2. 2.2 Queues
      1. 2.2.1 Packet Queuing
      2. 2.2.2 Packet De-queuing
      3. 2.2.3 Queue Proxy
    3. 2.3 Queue Types
      1. 2.3.1 Transmit Queues
      2. 2.3.2 Transmit Completion Queues
      3. 2.3.3 Receive Queues
      4. 2.3.4 Free Descriptor Queues (FDQ)
        1. 2.3.4.1 Host Packet Free Descriptors
        2. 2.3.4.2 Monolithic Free Descriptors
      5. 2.3.5 Queue Pend Queues
    4. 2.4 Descriptors
      1. 2.4.1 Host Packet
      2. 2.4.2 Host Buffer
      3. 2.4.3 Monolithic Packet
    5. 2.5 Packet DMA
      1. 2.5.1 Channels
      2. 2.5.2 RX Flows
    6. 2.6 Packet Transmission Overview
    7. 2.7 Packet Reception Overview
    8. 2.8 ARM Endianess
  4. 3Descriptor Layouts
    1. 3.1 Host Packet Descriptor
    2. 3.2 Host Buffer Descriptor
    3. 3.3 Monolithic Descriptor
  5. 4Registers
    1. 4.1 Queue Manager
      1. 4.1.1 Queue Configuration Region
        1. 4.1.1.1 Revision Register (0x00000000)
        2. 4.1.1.2 Queue Diversion Register (0x00000008)
        3. 4.1.1.3 Linking RAM Region 0 Base Address Register (0x0000000C)
        4. 4.1.1.4 Linking RAM Region 0 Size Register (0x00000010)
        5. 4.1.1.5 Linking RAM Region 1 Base Address Register (0x00000014)
        6. 4.1.1.6 Free Descriptor/Buffer Starvation Count Register N (0x00000020 + N×4)
      2. 4.1.2 Queue Status RAM
      3. 4.1.3 Descriptor Memory Setup Region
        1. 4.1.3.1 Memory Region R Base Address Register (0x00000000 + 16×R)
        2. 4.1.3.2 Memory Region R Start Index Register (0x00000004 + 16×R)
        3. 4.1.3.3 Memory Region R Descriptor Setup Register (0x00000008 + 16×R)
      4. 4.1.4 Queue Management/Queue Proxy Regions
        1. 4.1.4.1 Queue N Register A (0x00000000 + 16×N)
        2. 4.1.4.2 Queue N Register B (0x00000004 + 16×N)
        3. 4.1.4.3 Queue N Register C (0x00000008 + 16×N)
        4. 4.1.4.4 Queue N Register D (0x0000000C + 16×N)
      5. 4.1.5 Queue Peek Region
        1. 4.1.5.1 Queue N Status and Configuration Register A (0x00000000 + 16×N)
        2. 4.1.5.2 Queue N Status and Configuration Register B (0x00000004 + 16×N)
        3. 4.1.5.3 Queue N Status and Configuration Register C (0x00000008 + 16×N)
        4. 4.1.5.4 Queue N Status and Configuration Register D (0x0000000C + 16×N)
    2. 4.2 Packet DMA
      1. 4.2.1 Global Control Registers Region
        1. 4.2.1.1 Revision Register (0x00)
        2. 4.2.1.2 Performance Control Register (0x04)
        3. 4.2.1.3 Emulation Control Register (0x08)
        4. 4.2.1.4 Priority Control Register (0x0C)
        5. 4.2.1.5 QMn Base Address Register (0x10, 0x14, 0x18, 0x1c)
      2. 4.2.2 TX DMA Channel Configuration Region
        1. 4.2.2.1 TX Channel N Global Configuration Register A (0x000 + 32×N)
        2. 4.2.2.2 TX Channel N Global Configuration Register B (0x004 + 32×N)
      3. 4.2.3 RX DMA Channel Configuration Region
        1. 4.2.3.1 RX Channel N Global Configuration Register A (0x000 + 32×N)
      4. 4.2.4 RX DMA Flow Configuration Region
        1. 4.2.4.1 RX Flow N Configuration Register A (0x000 + 32×N)
        2. 4.2.4.2 RX Flow N Configuration Register B (0x004 + 32×N)
        3. 4.2.4.3 RX Flow N Configuration Register C (0x008 + 32×N)
        4. 4.2.4.4 RX Flow N Configuration Register D (0x00C + 32×N)
        5. 4.2.4.5 RX Flow N Configuration Register E (0x010 + 32×N)
        6. 4.2.4.6 RX Flow N Configuration Register F (0x014 + 32×N)
        7. 4.2.4.7 RX Flow N Configuration Register G (0x018 + 32×N)
        8. 4.2.4.8 RX Flow N Configuration Register H (0x01C + 32×N)
      5. 4.2.5 TX Scheduler Configuration Region
        1. 4.2.5.1 TX Channel N Scheduler Configuration Register (0x000 + 4×N)
    3. 4.3 QMSS PDSPs
      1. 4.3.1 Descriptor Accumulation Firmware
        1. 4.3.1.1 Command Buffer Interface
        2. 4.3.1.2 Global Timer Command Interface
        3. 4.3.1.3 Reclamation Queue Command Interface
        4. 4.3.1.4 Queue Diversion Command Interface
      2. 4.3.2 Quality of Service Firmware
        1. 4.3.2.1 QoS Algorithms
          1. 4.3.2.1.1 Modified Token Bucket Algorithm
        2. 4.3.2.2 Command Buffer Interface
        3. 4.3.2.3 QoS Firmware Commands
        4. 4.3.2.4 QoS Queue Record
        5. 4.3.2.5 QoS Cluster Record
        6. 4.3.2.6 RR-Mode QoS Cluster Record
        7. 4.3.2.7 SRIO Queue Monitoring
          1. 4.3.2.7.1 QoS SRIO Queue Monitoring Record
      3. 4.3.3 Open Event Machine Firmware
      4. 4.3.4 Interrupt Operation
        1. 4.3.4.1 Interrupt Handshaking
        2. 4.3.4.2 Interrupt Processing
        3. 4.3.4.3 Interrupt Generation
        4. 4.3.4.4 Stall Avoidance
      5. 4.3.5 QMSS PDSP Registers
        1. 4.3.5.1 Control Register (0x00000000)
        2. 4.3.5.2 Status Register (0x00000004)
        3. 4.3.5.3 Cycle Count Register (0x0000000C)
        4. 4.3.5.4 Stall Count Register (0x00000010)
    4. 4.4 QMSS Interrupt Distributor
      1. 4.4.1 INTD Register Region
        1. 4.4.1.1  Revision Register (0x00000000)
        2. 4.4.1.2  End Of Interrupt (EOI) Register (0x00000010)
        3. 4.4.1.3  Status Register 0 (0x00000200)
        4. 4.4.1.4  Status Register 1 (0x00000204)
        5. 4.4.1.5  Status Register 2 (0x00000208)
        6. 4.4.1.6  Status Register 3 (0x0000020c)
        7. 4.4.1.7  Status Register 4 (0x00000210)
        8. 4.4.1.8  Status Clear Register 0 (0x00000280)
        9. 4.4.1.9  Status Clear Register 1 (0x00000284)
        10. 4.4.1.10 Status Clear Register 4 (0x00000290)
        11. 4.4.1.11 Interrupt N Count Register (0x00000300 + 4xN)
  6. 5Mapping Information
    1. 5.1 Queue Maps
    2. 5.2 Interrupt Maps
      1. 5.2.1 KeyStone I TCI661x, C6670, C665x devices
      2. 5.2.2 KeyStone I TCI660x, C667x devices
      3. 5.2.3 KeyStone II devices
    3. 5.3 Memory Maps
      1. 5.3.1 QMSS Register Memory Map
      2. 5.3.2 KeyStone I PKTDMA Register Memory Map
      3. 5.3.3 KeyStone II PKTDMA Register Memory Map
    4. 5.4 Packet DMA Channel Map
  7. 6Programming Information
    1. 6.1 Programming Considerations
      1. 6.1.1 System Planning
      2. 6.1.2 Notification of Completed Work
    2. 6.2 Example Code
      1. 6.2.1 QMSS Initialization
      2. 6.2.2 PKTDMA Initialization
      3. 6.2.3 Normal Infrastructure DMA with Accumulation
      4. 6.2.4 Bypass Infrastructure notification with Accumulation
      5. 6.2.5 Channel Teardown
    3. 6.3 Programming Overrides
    4. 6.4 Programming Errors
    5. 6.5 Questions and Answers
  8. AExample Code Utility Functions
  9. BExample Code Types
  10. CExample Code Addresses
    1. C.1 KeyStone I Addresses:
    2. C.2 KeyStone II Addresses:
  11.   Revision History

5.1 Queue Maps

The queue manager supports a total of 8192 queues (16k for KeyStone II). Most of them are available for general purpose use, but some are dedicated for special use, and in some cases, have special hardware functionality associated with them. Queues not listed are general purpose queues.

NOTE

Any queue that is not used by the application for hardware purposes may be used as a general purpose queue. You must only ensure that the corresponding hardware functionality is not enabled. For example, if Low Priority accumulation is not used, queues 0 to 511 may be used as general purpose queues.

Table 5-1 Queue Map for KeyStone I

TCI6616 Queues TCI660x/ C667x Queues TCI6618/ C6670 Queues TCI6614 Queues C665x Queues Purpose
0 to 511 (512) Same Same Same Same Normally used by low priority accumulation. The low priority accumulator uses up to 512 queues divided into 16 channels, each channel being 32 continuous queues. Each channel triggers one broadcast interrupt. These queues can also be used as general purpose queues.
512 to 639 (128) Same Same Same AIF2 TX queues. Each queue has a dedicated queue pending signal that drives a TX DMA channel.
640 to 648 (9) Same Same Same NetCP TX queues. Each queue has a dedicated queue pending signal that drives a TX DMA channel.
650-657 (8) ARM queue pend queues. These queues have dedicated queue pending signals wired directly to the ARM.
662 to 671 (10) 652 to 671 (20) 662 to 671 (10) 662 to 671 (10) INTC0/INTC1 queue pend queues. These queues have dedicated queue pending signals wired directly into the chip level INTC0 and/or INTC1. Note that the event mapping can differ for each device.
670-671 (2) ARM queue pend queues. These queues have dedicated queue pending signals wired directly to the ARM. Note that these are also routed to INTC0.
672 to 687 (16) Same Same Same Same SRIO TX queues. Each queue has a dedicated queue pending signal that drives a TX DMA channel.
688 to 695 (8) Same Same Same FFTC_A, B TX queues. Each queue has a dedicated queue pending signal that drives a TX DMA channel.
704 to 735 (32) Same Same Same Same Normally used by high priority accumulation. The high priority accumulator uses up to 32 queues, one per channel. Each channel triggers a core-specific interrupt. These queues can also be used as general purpose queues.
736 to 799 (64) Same Same Same Same Queues with starvation counters readable by the host. Starvation counters increment each time a pop is performed on an empty queue, and reset when the starvation count is read.
800 to 831 (32) Same Same Same Same QMSS TX queues. Used for infrastructure (core to core) DMA copies and notification.
832 to 863 (32) Same Same Same Same General purpose queues, or may be configured for use by QoS traffic shaping firmware.
864 to 867 (4) FFTC_C TX queues. Each queue has a dedicated queue pending signal that drives a TX DMA channel.
864 to 895 (32) Same Same Same Same HyperLink queue pend queues. These queues have dedicated queue pending signals wired directly into HyperLink. On some devices, these overlap. They cannot be simultaneously used for both IP (i.e. use queue 864 for either FFTC_C or Hyperlink).
868 to 875 (8) 864 to 871 (8) BCP TX queues. Each queue has a dedicated queue pending signal that drives a TX DMA channel. Also routed to HyperLink.
896 to 8191 Same Same Same Same General purpose. Due to the mapping of logical to physical queues in the PKTDMA interfaces, the use of 0xFFF in PKTDMA qnum fields is reserved to specify non-override conditions.

Table 5-2 Queue Map for KeyStone II

K2K Queues K2H Queues K2L Queues K2E Queues Purpose
0 to 511 (512) Same Same Same Normally used by low priority accumulation. The low priority accumulator uses up to 512 queues divided into 16 channels, each channel being 32 continuous queues. Each channel triggers one broadcast interrupt. These queues can also be used as general purpose queues.
512 to 639 (128) Same AIF2 TX queues. Each queue has a dedicated queue pending signal that drives a TX DMA channel.
560 to 569 (10) Same EDMA0 queue pend queues.
640 to 648 (9) Same 896 to 1023 (128) Same (896 to 1023) NetCP TX queues. Each queue has a dedicated queue pending signal that drives a TX DMA channel.
528 to 559 (32), 652 to 671 (20) Same 570 to 687 (118) 652 to 691 (40) Broadcast CICx/SOC queue pend queues. These queues have dedicated queue pending signals wired directly into the chip level interrupt controllers.
672 to 687 (16) Same SRIO TX queues. Each queue has a dedicated queue pending signal that drives a TX DMA channel.
688 to 695(8) Same Same FFTC_A, B TX queues. Each queue has a dedicated queue pending signal that drives a TX DMA channel.
704 to 735 (32) Same Same Same Normally used by high priority accumulation. The high priority accumulator uses up to 32 queues, one per channel. Each channel triggers a core-specific interrupt. These queues can also be used as general purpose queues.
736 to 799 (64) Same Same Same Queues with starvation counters readable by the host. Starvation counters increment each time a pop is performed on an empty queue, and reset when the starvation count is read.
800 to 831 (32) Same Same Same QMSS TX queues for PKTDMA1. Used for infrastructure (core to core) DMA copies and notification.
832 to 863 (32) Same General purpose queues, or may be configured for use by QoS traffic shaping firmware.
Same 832 to 879 (48) IQN2 TX queues.
864 to 871 (8) Same 696 to 703 (8) BCP TX queues. Each queue has a dedicated queue pending signal that drives a TX DMA channel.
872 to 887 (16) Same FFTC_C, _D, _E, and _F TX queues (four per FFTC). Each queue has a dedicated queue pending signal that drives a TX DMA channel.
8192 to 8703 (512) Same Normally used by low priority accumulation for QM2. The low priority accumulator uses up to 512 queues divided into 16 channels, each channel being 32 continuous queues. Each channel triggers one broadcast interrupt. These queues can also be used as general purpose queues.
8704 to 8735 (32) Same 528 to 559 (32) Same (528 to 559) ARM Interrupt controller queue pend queues.
589, 590 570 to 580 (11) EDMA1 queue pend queues.
591 to 602 (12) 581 to 588 (8) EDMA2 queue pend queues.
603, 604 589 to 604 (16) EDMA3 queue pend queues.
8736 to 8743(8) Same 605-612 (8) EDMA4 queue pend queues.
8744 to 8751(8) Same HyperLink broadcast queue pend queues.
8752 to 8759 (8) Same 692 to 699 (8) XGE queue pend queues.
8796 to 8811 (16) Same 613 to 636 (24) HyperLink 0 queue pend queues.
8812 to 8843 (32) Same DXB queue pend queues.
8844 to 8863 (20) Same INTC0/C1/C2 queue pend queues. These queues have dedicated queue pending signals wired directly into the chip level interrupt controllers.
8864 to 8879 (16) Same HyperLink 1 queue pend queues.
8896 to 8927 (32) Same Normally used by high priority accumulation for QM2. The high priority accumulator uses up to 32 queues, one per channel. Each channel triggers a core-specific interrupt. These queues can also be used as general purpose queues.
8928 to 8991 (64) Same Queues with starvation counters readable by the host. Starvation counters increment each time a pop is performed on an empty queue, and reset when the starvation count is read.
8992 to 9023 (32) Same QMSS TX queues for PKTDMA2. Used for infrastructure (core to core) DMA copies and notification.
9024 to 16383 Same General purpose queues.