SPRAAV1C May   2009  – March 2020 AM3703 , AM3715 , OMAP3503 , OMAP3515 , OMAP3525 , OMAP3530

 

  1.   PCB Design Guidelines for 0.4mm Package-On-Package (PoP) Packages, Part I
    1.     Trademarks
    2. 1  Using This Guide
    3. 2  A Word of Caution
    4. 3  A Team Sport
    5. 4  Be Wary of Quotes
    6. 5  Don’t Forget Your CAD Tools
    7. 6  Metric Vs English
    8. 7  PCB Fab Limits
    9. 8  Routing and Layer Stackup
    10. 9  OMAP35x 0.4mm Pitch
    11. 10 Pad Type
    12. 11 PCB Pad Dimensions for 0.4mm BGA Package
    13. 12 Multiple BGA Packages
    14. 13 Etch Traps and Heat Sinks
    15. 14 Vias and VIP
    16. 15 Laser Blind Vias
    17. 16 Filled Vias
    18. 17 Know Your Tools
    19. 18 BeagleBoard
    20. 19 BeagleBoard Views
      1. 19.1 Top Layer – Signal - Area Underneath the OMAP35x
      2. 19.2 Layer 2 – Ground
      3. 19.3 Layer 3 – Signal
      4. 19.4 Layer 4 – Signal
      5. 19.5 Layer 5 – Power (VDD2)
      6. 19.6 Layer 6 – Signal – Bottom Copper – Bottom Component Outlines
    21. 20 OMAP35x Decoupling
    22. 21 PCB Finishes for High Density Interconnect (HDI)
    23. 22 Real World Second Opinion
    24. 23 Acknowledgments
    25. 24 References
  2.   Revision History

8 Routing and Layer Stackup

One huge benefit of PoP is the elimination of the high-speed, balanced transmission lines between the processor and memory. The external memory’s data and control lines no longer have to be routed out from under the processor. This is a huge savings in both time and the number of layers. This also impacts your pad and layer stackup decisions. OEMs have quickly adopted PoP as their processor/memory package of choice for these reasons.

It is possible to use a 6-layer stack and route all of the connections without requiring buried vias. For the BeagleBoard, relatively common VIP technology was used. There are several suitable layer setups; the one described below was used in the BeagleBoard. This format is also popular because it allows sensitive clock signals or relatively high-speed lines to be routed between power planes.

Layer 1 Signal (Top Copper)
Layer 2 Ground
Layer 3 Signal
Layer 4 Signal
Layer 5 Power
Layer 6 Signal (Bottom Copper)

Package footprints and pad stacks are the next important item to consider. Proper definitions and strict adherence to clearance plays a key role in the development of high yield PoP designs.