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参数

Arm CPU 1 Arm Cortex-A8 Arm MHz (Max.) 720 Co-processor(s) GPU, DSP CPU 32-bit Display type Parallel Digital Output, Up to 24-Bit RGB Compatible, HD Maximum Resolution ?? ETM Interface, Supports Up to 2 LCD Panels, Support for Remote Frame Buffer, Interface (RFBI) LCD Panels Operating system Linux, RTOS Rating Catalog Operating temperature range (C) -40 to 105, 0 to 90 open-in-new 查找其它 基于 Arm 的处理器

封装|引脚|尺寸

FC/CSP (CUS) 423 256 mm² 16 x 16 POP-FCBGA (CBB) 515 144 mm² 12 x 12 open-in-new 查找其它 基于 Arm 的处理器

特性

  • OMAP3530 and OMAP3525 Devices:
    • OMAP™ 3 Architecture
    • MPU Subsystem
      • Up to 720-MHz ARM® Cortex™-A8 Core
      • NEON™ SIMD Coprocessor
    • High-Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem
      • Up to 520-MHz TMS320C64x+™ DSP Core
      • Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
      • Video Hardware Accelerators
    • PowerVR® SGX™ Graphics Accelerator (OMAP3530 Device Only)
      • Tile-Based Architecture Delivering up to 10 MPoly/sec
      • Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Programmable High-Quality Image Anti-Aliasing
    • Fully Software-Compatible with C64x and ARM9™
    • Commercial and Extended Temperature Grades
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+ DSP Core
    • Eight Highly Independent Functional Units
      • Six ALUs (32- and 40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture with Nonaligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ L1 and L2 Memory Architecture
    • 32KB of L1P Program RAM and Cache (Direct Mapped)
    • 80KB of L1D Data RAM and Cache (2-Way Set-Associative)
    • 64KB of L2 Unified Mapped RAM and Cache (4-Way Set-Associative)
    • 32KB of L2 Shared SRAM and 16KB of L2 ROM
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • TrustZone®
      • Thumb®-2
      • MMU Enhancements
    • In-Order, Dual-Issue, Superscalar Microprocessor Core
    • NEON Multimedia Architecture
    • Over 2x Performance of ARMv6 SIMD
    • Supports Both Integer and Floating-Point SIMD
    • Jazelle® RCT Execution Environment Architecture
    • Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
    • Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
  • ARM Cortex-A8 Memory Architecture:
    • 16-KB Instruction Cache (4-Way Set-Associative)
    • 16-KB Data Cache (4-Way Set-Associative)
    • 256-KB L2 Cache
  • 112KB of ROM
  • 64KB of Shared SRAM
  • Endianess:
    • ARM Instructions – Little Endian
    • ARM Data – Configurable
    • DSP Instruction and Data - Little Endian
  • External Memory Interfaces:
    • SDRAM Controller (SDRC)
      • 16- and 32-Bit Memory Controller with 1GB of Total Address Space
      • Interfaces to Low-Power Double Data Rate (LPDDR) SDRAM
      • SDRAM Memory Scheduler (SMS) and Rotation Engine
    • General Purpose Memory Controller (GPMC)
      • 16-Bit-Wide Multiplexed Address and Data Bus
      • Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin
      • Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM
      • Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
      • Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
  • System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
  • Camera Image Signal Processor (ISP)
    • CCD and CMOS Imager Interface
    • Memory Data Input
    • BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
    • Glueless Interface to Common Video Decoders
    • Resize Engine
      • Resize Images From 1/4x to 4x
      • Separate Horizontal and Vertical Control
  • Display Subsystem
    • Parallel Digital Output
      • Up to 24-Bit RGB
      • HD Maximum Resolution
      • Supports Up to 2 LCD Panels
      • Support for Remote Frame Buffer Interface (RFBI) LCD Panels
    • 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
      • Composite NTSC and PAL Video
      • Luma and Chroma Separate Video (S-Video)
    • Rotation 90-, 180-, and 270-Degrees
    • Resize Images From 1/4x to 8x
    • Color Space Converter
    • 8-Bit Alpha Blending
  • Serial Communication
    • 5 Multichannel Buffered Serial Ports (McBSPs)
      • 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
      • 5-KB Transmit and Receive Buffer (McBSP2)
      • SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
      • Direct Interface to I2S and PCM Device and TDM Buses
      • 128-Channel Transmit and Receive Mode
    • Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
    • High-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)
    • High-, Full-, and Low-Speed Multiport USB Host Subsystem
      • 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface
      • Supports Transceiverless Link Logic (TLL)
    • One HDQ™/1-Wire® Interface
    • Three UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
    • Three Master and Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
  • Removable Media Interfaces:
    • Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
  • Comprehensive Power, Reset, and Clock Management
    • SmartReflex™ Technology
    • Dynamic Voltage and Frequency Scaling (DVFS)
  • Test Interfaces
    • IEEE 1149.1 (JTAG) Boundary-Scan Compatible
    • ETM Interface
    • Serial Data Transport Interface (SDTI)
  • 12 32-Bit General-Purpose Timers
  • 2 32-Bit Watchdog Timers
  • 1 32-Bit 32-kHz Sync Timer
  • Up to 188 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • 65-nm CMOS Technologies
  • Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
  • Discrete Memory Interface (Not Available in CBC Package)
  • Packages:
    • 515-pin s-PBGA Package (CBB Suffix),
      .5-mm Ball Pitch (Top), .4-mm Ball Pitch (Bottom)
    • 515-pin s-PBGA Package (CBC Suffix),
      .65-mm Ball Pitch (Top), .5-mm Ball Pitch (Bottom)
    • 423-pin s-PBGA Package (CUS Suffix),
      .65-mm Ball Pitch
  • 1.8-V I/O and 3.0-V (MMC1 Only),
    0.985-V to 1.35-V Adaptive Processor Core Voltage
    0.985-V to 1.35-V Adaptive Core Logic Voltage
    Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.
open-in-new 查找其它 基于 Arm 的处理器

描述

OMAP3530 and OMAP3525 devices are based on the enhanced OMAP 3 architecture.

The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

  • Streaming video
  • Video conferencing
  • High-resolution still image

The device supports high-level operating systems (HLOSs), such as:

  • Linux®
  • Windows® CE
  • Android™

This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

The following subsystems are part of the device:

  • Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor
  • IVA2.2 subsystem with a C64x+ digital signal processor (DSP) core
  • PowerVR SGX subsystem for 3D graphics acceleration to support display (OMAP3530 device only)
  • Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors
  • Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC and PAL video out.
  • Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

  • A comprehensive power- and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex adaptative voltage control. This power-management technique for automatic control of the operating voltage of a module reduces the active power consumption.
  • Memory-stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only)

OMAP3530 and OMAP3525 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences).

This data manual presents the electrical and mechanical specifications for the OMAP3530 and OMAP3525 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP3530 and OMAP3525 applications processors unless otherwise indicated. This data manual consists of the following sections:

  • Section 2: Terminal Description: assignment, electrical characteristics, multiplexing, and functional description
  • Section 3: Electrical Characteristics: power domains, operating conditions, power consumption, and DC characteristics
  • Section 4: Clock Specifications input and output clocks, DPLL and DLL
  • Section 5: Video Dac Specifications
  • Section 6: Timing Requirements and Switching Characteristics
  • Section 7: Package Characteristics: thermal characteristics, device nomenclature, and mechanical data for available packaging
open-in-new 查找其它 基于 Arm 的处理器
下载

No design support from TI available

This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

技术文档

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类型 标题 下载最新的英文版本 日期
* 数据表 OMAP3530/25 Applications Processor 数据表 (Rev. H) 2013年 10月 10日
* 勘误表 OMAP3530/25/15/03 Applications Processor Silicon Errata-Revs 3.1, 3.0, 2.1,&2.0 (Rev. F) 2010年 10月 12日
用户指南 SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 2020年 6月 1日
应用手册 PCB Design Guidelines for 0.4mm Package-On-Package (PoP) Packages, Part I (Rev. C) 2020年 3月 3日
应用手册 TMS320C6472 DDR2 Implementation Guidelines 2019年 3月 20日
技术文章 Bringing the next evolution of machine learning to the edge 2018年 11月 27日
技术文章 Industry 4.0 spelled backward makes no sense – and neither does the fact that you haven’t heard of TI’s newest processor yet 2018年 10月 30日
技术文章 How quality assurance on the Processor SDK can improve software scalability 2018年 8月 22日
技术文章 Clove: Low-Power video solutions based on Sitara™ AM57x processors 2016年 7月 21日
应用手册 PCB Assembly Guidelines for 0.4mm Package-On-Package (PoP) Packages, Part II (Rev. A) 2013年 11月 1日
更多文献资料 Picture it: DSPs in medical imaging (Rev. C) 2013年 7月 12日
用户指南 Delta for OMAP35x Technical Reference Manual Version X to Version Y (Rev. Y) 2012年 12月 10日
用户指南 OMAP35x Technical Reference Manual (Rev. Y) 2012年 12月 10日
应用手册 Power Consumption Guide for the C66x 2011年 10月 6日
应用手册 使用 TPS65023 为 OMAP™3 供电:设计指南 (Rev. B) 2010年 10月 8日
用户指南 使用 TPS65950 为 OMAP™3 供电:设计用户指南 (Rev. C) 下载英文版本 (Rev.C) 2010年 10月 8日
应用手册 Assembly Guidelines for 0.5mm Package-on-Package(PoP) Packages, Part II 2010年 6月 23日
应用手册 PCB Design Guidelines for 0.5mm Package-On-Package (PoP) Packages, Part I 2010年 6月 23日
应用手册 OMAP35x to AM37x Hardware Migration Guide 2010年 6月 3日
应用手册 OMAP35x to AM35x Hardware Migration Guide 2010年 5月 24日
应用手册 OMAP3530 Easy CUS Package PCB Escape Routing (Rev. A) 2010年 3月 25日
用户指南 OMAP35x Peripherals Overview Reference Guide (Rev. A) 2010年 1月 20日
应用手册 OMAP3530 Power Estimation Spreadsheet 2010年 1月 8日
应用手册 OMAP35x Linux PSP Data Sheet 2009年 10月 16日
用户指南 Powering OMAP35x with TPS65073x 2009年 10月 13日
应用手册 Running a TMS320C64x+ Codec Across TMS320C64x+ Based DSP Platforms 2009年 9月 24日
应用手册 Color Scan Conversion 2009年 4月 3日
应用手册 OMAP35x 0.65mm Pitch Layout Methods (Rev. B) 2008年 6月 26日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

软件开发

软件开发套件 (SDK) 下载
用于 Sitara 微处理器的 Android 开发套件
ANDROIDSDK-SITARA 虽然起初专为移动手持终端而设计,Android 操作系统仍允许嵌入式应用的设计人员轻松为产品增加高级操作系统。 与 Google 联合开发的 Android 是一套可立即实现集成和生产的全面操作系统。


Android 操作系统的亮点在于:

  • 完整的开放源码软件解决方案
  • 基于 Linux
  • 针对商业开发的简洁许可条款 (Apache)
  • 包含一个完整的应用框架
  • 允许通过 Java 轻松集成定制开发应用
  • 开包即用的多媒体、图形和图形用户界面
  • 大量 Android 和应用开发人员供随时调遣

 

特性

TI 的 Android 开发套件是一套完整的软件,Sitara 器件的开发人员可以用其轻松快速地评估 Android 操作系统。该套件提供稳定且经全面测试的软件基础,可广泛用于包括评估模块和 Beagleboard (beagleboard.org) 在内的各种 Sitara 硬件。


该开发套件包含:

  • Linux 内核
  • Uboot/x 加载程序
  • 3D 图形 OpenGL(r) 驱动程序和库
  • 用于 Android 的 Adobe Flash 10 库
  • RowboPERF,性能基准应用
  • 包括 3D 图形的示例应用
  • 主机工具
  • 调试选项
  • 完整文档


其它集成功能,例如对 WLAN、Bluetooth(R)、S 视频、分量视频、快速启动、电源管理、NAND UBIFS、摄像机、HDMI、Gb (...)

代码示例或演示 下载
软件编解码器 下载
编解码器 - 视频和语音 - 基于 C64x+ 的器件(OMAP35x、C645x、C647x、DM646、DM644x 和 DM643x)
C64XPLUSCODECS TI 编解码器免费提供,附带生产许可且现在可供下载。全部经过生产测试,可轻松地集成到音频、视频和语音应用中 单击“获取软件”按钮(上方),以获取经过测试的最新编解码器版本。该页面及每个安装程序中都包含有数据表和发布说明。

 

 

其它信息:

特性

为获得最佳的设计效果,请查找针对您平台进行优化的编解码器。如果找不到,请单击“获取软件”按钮(上方)查找针对 TI C64x+ 内核器件(例如:OMAP35x、TMS320C645x、TMS320C647x、TMS320DM646x、TMS320DM644x 和 TMS320DM643x 系列的大多数器件)进行优化的编解码器。

 

C64x+ 编解码器提供:

  • (...)
软件编解码器 下载
编解码器 - 针对 OMAP35x 处理器进行了优化
OMAP35XCODECS TI 编解码器免费提供,附带生产许可且现在可供下载。全部经过生产测试,可轻松集成到音频、视频和语音应用中。单击“获取软件”按钮(上方),以获取经过测试的最新编解码器版本。该页面及每个安装程序中都包含有数据表和发布说明。

 

 

附加信息

 

特性

OMAP35x 编解码器经过优化,可用于 OMAP3525 和 OMAP3530 处理器。为获得最佳的设计效果,请使用这些。如果您要搜索其它 TI 编解码器,请查找针对 TI C64x+ 内核器件(例如:OMAP35x、TMS320C645x、TMS320C647x、TMS320DM646x、TMS320DM644x 和 (...)

软件编程工具 下载
用于 AM35x、AM37x、DM37x 和 OMAP35x 器件的 FlashTool
FLASHTOOL — Flash Tool is a Windows-based application that can be used to transfer binary images from a host PC to TI Sitara AM35x, AM37x, DM37x and OMAP35x target platforms.


Additional Information:

TI GForge - Welcome to gforge.ti.com

TI E2E Community

设计工具和仿真

仿真模型 下载
SPRM314B.ZIP (10 KB) - BSDL Model
仿真模型 下载
SPRM315C.ZIP (11 KB) - BSDL Model
仿真模型 下载
SPRM322A.ZIP (1575 KB) - IBIS Model
仿真模型 下载
SPRM323A.ZIP (1559 KB) - IBIS Model
仿真模型 下载
SPRM324B.ZIP (1537 KB) - IBIS Model
仿真模型 下载
SPRM346A.ZIP (10 KB) - BSDL Model
计算工具 下载
计算工具 下载
特性

功耗估算工具 (PET)

步骤 1.

下载并填写输入电子表格。
将其另存为 Excel 2003 格式。

对于 OMAP35x 处理器

下载 OMAP35x 的简化电子表格

下载 OMAP35x 的高级电子表格

对于 AM35x ARM Cortex™-A8 微处理器

下载 AM35x 的简化电子表格

下载 AM35x 的高级电子表格

对于 AM335x ARM Cortex™-A8 微处理器

下载 AM335x 的简化电子表格

下载 AM335x 的高级电子表格

步骤 2.

上传电子表格。
需要登录。

上传电子表格

步骤 3.

通过电子邮件向您发送功耗估算报告。
查看取样报告

PET 使用户能够深入了解所选 Sitara 和 OMAP 处理器的功耗。该工具能让用户选择多种应用方案,并让他们了解功耗以及如何应用高级节能技术以进一步降低整体功耗。

PET 包括三个模块:

  1. 下载输入电子表格 - 这种可下载的电子表格是一种能够让用户输入其应用所需的器件参数的机制。参数包括 IP 活动/加载、所需电源状态以及电源管理使用。多种操作条件可随时隙一起应用于各种状态。
  2. 上传电子表格 - 完成输入电子表格之后,用户便可以向 TI 上传电子表格,以便进行功耗分析。上传需要注册和接受法律协议。
  3. 功耗估算报告 - 包含根据上传的电子表格生成的功耗信息。报告包括信息泄漏、活动功耗、总体平均功耗以及电源管理电压;如果使用了 Smart Reflex,则将通过电子邮件向用户报告。

在以下维客位置可以找到有关 PET 的详细信息:

设计工具 下载
Arm-based MPU, arm-based MCU and DSP third-party search tool
PROCESSORS-3P-SEARCH TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI Processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
特性
  • Supports many TI processors including Sitara and Jacinto Processors and DSPs
  • Search by type of product, TI devices supported, or country
  • Links and contacts for quick engagement
  • Third-party companies located around the world

CAD/CAE 符号

封装 引脚 下载
FCBGA (CUS) 423 了解详情
POP-FCBGA (CBB) 515 了解详情

订购与质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/FIT 估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

支持与培训

可获得 TI E2E™ 论坛的工程师技术支持

所有内容均由 TI 和社区网友按“原样”提供,并不构成 TI 规范。参阅使用条款

如果您对质量、包装或订购 TI 产品有疑问,请参阅 TI 支持

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