SLAU367P October 2012 – April 2020
eUSCI_Bx Interrupt Flag Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Reserved | |||||||
| r0 | r0 | r0 | r0 | r0 | r0 | r0 | r0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reserved | UCTXIFG | UCRXIFG | |||||
| r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | rw-1 | rw-0 |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-2 | Reserved | R | 0h |
Reserved |
| 1 | UCTXIFG | RW | 1h |
Transmit interrupt flag. UCTXIFG is set when UCxxTXBUF empty. 0b = No interrupt pending 1b = Interrupt pending |
| 0 | UCRXIFG | RW | 0h |
Receive interrupt flag. UCRXIFG is set when UCxxRXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending |