SBAK043 April   2026 DAC39RF10-SP , DAC39RFS10-SP

 

  1.   1
  2.   2
  3.   Trademarks
  4. 1Introduction
  5. 2Single-Event Effects
  6. 3Device and Test Board Information
  7. 4Irradiation Facility and Setup
  8. 5Test Setup and Procedures
  9. 6Single-Event Latch-Up (SEL) Results
  10. 7Single-Event Functional Interrupt (SEFI) Results
    1. 7.1 Converter Performance and Digital (DUC + JESD204C Link) Hardness
    2. 7.2 Configuration Register Hardness
    3. 7.3 SPI Programming During Irradiation
  11. 8SEU Results
    1. 8.1 JESD204C Link Monitoring Results
    2. 8.2 Digital Up-Converter and NCO Upset Recovery
    3. 8.3 Estimating Upset Rates in Unprotected Data Paths
    4. 8.4 Event Rate Calculations
    5. 8.5 Summary of Radiation Hardness
  12. 9References
  13.   A Appendix: Recommendations for Hi-Rel Systems
    1.     A.1 Summary of Rad-Hard Design Features
    2.     A.2 SPI Programming
    3.     A.3 JESD204C Reliability
    4.     A.4 Equalizer Usage in Radiation Environments
    5.     A.5 NCO Reliability
    6.     A.6 NCO Frequency and Phase Correction (Strategy #1)
    7.     A.7 NCO Frequency Correction (Strategy #2)
    8.     A.8 NCO Self-Sync/Self-Coherent Mode (Strategy #3)

A.8 NCO Self-Sync/Self-Coherent Mode (Strategy #3)

This strategy uses an internal counter to continuously self-synchronize the NCOs and also configures all four NCOs to share a common phase reference counter. This protects the frequency of all NCOs and protects the phase difference between all NCOs (by sharing a common reference). In DDS mode, it also protects the amplitude setting of each NCO. This mode is appropriate for a multi-DUC, phased-array system utilizing a single DAC39RF10-SP part. It is also appropriate for applications that use the DAC to generate tones and do not want to provide a SYSREF signal. It can also be used in DDS mode applications, specifically ones that use multiple NCOs to cancel out harmonics in the DAC or external amplifier (where phase coherency between NCOs must be maintained).

  1. Program NCO_AR = 0 to configure the accumulator to NOT be reset by a synchronization event.
  2. Configure the NCOs for self-coherent mode by setting NCO_SC = 1.
  3. Configure the NCOs for self-synchronizing mode by setting NCO_SS = 1.
  4. While the NCO is operating, any upset to its frequency or phase will be corrected on the next internal synchronization event (see NCO_SS). If the shared reference counter is upset, all NCOs will experience a phase jump but will maintain coherency with respect to each other (they share a common reference counter).