To estimate the upset rate of the DAC39RF10-SP, we again performed tests with the NCOs running without employing any hi-rel mitigation strategies. The goal was to understand and quantify how often the unprotected, high-speed circuitry saw an upset (as noted previously, these events were undetectable with hi-rel mitigation strategies employed). If the scope trigger was lost on the output tones being monitored, we recorded the fluence at which this event occurred and then used this data to estimate the device cross section.

To reemphasize, the hardened configuration registers do not experience upset conditions. Also, single events in the analog (for example, in the clocking path or analog DAC cores) flushed out of the data path in a few clock cycles.