SBAK043 April   2026 DAC39RF10-SP , DAC39RFS10-SP

 

  1.   1
  2.   2
  3.   Trademarks
  4. 1Introduction
  5. 2Single-Event Effects
  6. 3Device and Test Board Information
  7. 4Irradiation Facility and Setup
  8. 5Test Setup and Procedures
  9. 6Single-Event Latch-Up (SEL) Results
  10. 7Single-Event Functional Interrupt (SEFI) Results
    1. 7.1 Converter Performance and Digital (DUC + JESD204C Link) Hardness
    2. 7.2 Configuration Register Hardness
    3. 7.3 SPI Programming During Irradiation
  11. 8SEU Results
    1. 8.1 JESD204C Link Monitoring Results
    2. 8.2 Digital Up-Converter and NCO Upset Recovery
    3. 8.3 Estimating Upset Rates in Unprotected Data Paths
    4. 8.4 Event Rate Calculations
    5. 8.5 Summary of Radiation Hardness
  12. 9References
  13.   A Appendix: Recommendations for Hi-Rel Systems
    1.     A.1 Summary of Rad-Hard Design Features
    2.     A.2 SPI Programming
    3.     A.3 JESD204C Reliability
    4.     A.4 Equalizer Usage in Radiation Environments
    5.     A.5 NCO Reliability
    6.     A.6 NCO Frequency and Phase Correction (Strategy #1)
    7.     A.7 NCO Frequency Correction (Strategy #2)
    8.     A.8 NCO Self-Sync/Self-Coherent Mode (Strategy #3)

A.2 SPI Programming

The SPI interface and register set are implemented with upset-immune logic. The state of writable SPI registers will not be altered by radiation. The Fast-Reconfiguration interface is not upset-immune and should not be enabled in radiation environments.