SBAK043 April   2026 DAC39RF10-SP , DAC39RFS10-SP

 

  1.   1
  2.   2
  3.   Trademarks
  4. 1Introduction
  5. 2Single-Event Effects
  6. 3Device and Test Board Information
  7. 4Irradiation Facility and Setup
  8. 5Test Setup and Procedures
  9. 6Single-Event Latch-Up (SEL) Results
  10. 7Single-Event Functional Interrupt (SEFI) Results
    1. 7.1 Converter Performance and Digital (DUC + JESD204C Link) Hardness
    2. 7.2 Configuration Register Hardness
    3. 7.3 SPI Programming During Irradiation
  11. 8SEU Results
    1. 8.1 JESD204C Link Monitoring Results
    2. 8.2 Digital Up-Converter and NCO Upset Recovery
    3. 8.3 Estimating Upset Rates in Unprotected Data Paths
    4. 8.4 Event Rate Calculations
    5. 8.5 Summary of Radiation Hardness
  12. 9References
  13.   A Appendix: Recommendations for Hi-Rel Systems
    1.     A.1 Summary of Rad-Hard Design Features
    2.     A.2 SPI Programming
    3.     A.3 JESD204C Reliability
    4.     A.4 Equalizer Usage in Radiation Environments
    5.     A.5 NCO Reliability
    6.     A.6 NCO Frequency and Phase Correction (Strategy #1)
    7.     A.7 NCO Frequency Correction (Strategy #2)
    8.     A.8 NCO Self-Sync/Self-Coherent Mode (Strategy #3)

A.1 Summary of Rad-Hard Design Features

Feature Radiation Hardening
Writable SPI registers (excluding write-to-clear registers) Implemented with upset-immune flip-flops. Radiation will not alter their state.
Read-only SPI registers that return constant values Radiation will not alter their state (for example, CHIP_TYPE, CHIP_ID, CHIP_VERSION, VENDOR_ID).
Read-only SPI status registers associated with JESD204C physical or link layers (excluding write-to-clear registers) The value returned may be affected by radiation (SYSREF_POS, LINK_UP, JSYNC_STATE, PLL_LOCKED, LANE_ARR, FIFO_STATUS, JCAP_STATUS, JCAP, BER_CNT, LANE_EQS, ESDONE, ESVO_S, ECOUNT, RXDMUX, CDRPHASE, RXCSA_S).
FUSE_DONE register FUSE_DONE is upset-immune.
OCSTS register Once the PHY is initialized and offset calibration is completed, OCSTS returns offset values that are upset-immune. However, an upset can cause a PHY PLL to lose lock which can re-trigger the offset calibration process, generating new offset calibration values.
Sticky SPI status registers (write-to-clear) These bits get set when certain events occur in upset-vulnerable logic. An upset can cause the event to occur and set the sticky bit. An upset may also prevent an event from setting the sticky bit, however this is unlikely as the window of time that this can occur is very small. Once the sticky bit is set, an upset will not clear it (the flop that is read by SPI is upset immune).Examples: LANE_ERR, PLL_LOCK_LOST, SYS_ALM, REALIGNED, CLK_REALIGNED
JESD204C receiver The JESD204C receiver is not upset-immune, but is designed to be free from functional interrupts (can recover automatically from upsets). See JESD204C Reliability section below.
Interpolation filters (DUC and DES2X filters) The interpolation filters are not upset-immune and will generate glitches when upset. They do not suffer from functional interrupts.
NCOs in DUCs See NCO Reliability section below.
Temperature sensor The ADC inside the temperature sensor is not upset-immune. To improve reliability, it is recommended that TS_TEMP be read 3 or more times and the median value computed.