3 Device and Test Board Information

The DAC39RF10-SP is packaged in a 256-pin FCBGA (TI package code ACL) organic substrate flip-chip package. The device under test (DUT) was tested in a high-frequency capable, open-top socket using a custom characterization board similar to the DAC39RF10EVM evaluation board. To test the DAC in functional modes, the DAC EVM is mated to TI’s TSW14J59EVM FPGA capture card and pattern generator through an FMC+ connector.

Figure 3-2 shows the top view of the evaluation board and socket used for SEE testing.

The DAC39RF10-SP is a flip-chip device, so heavy ion irradiation is done from the backside of the die. The metal lid was removed from the DUT to expose the die surface, then the silicon is lapped from the standard 775μm down to 50μm (target final thickness) to allow for beam penetration into the active area of the die. An example thickness profile is shown in Figure 3-1.

Figure 3-1 Silicon Thickness Profile of DUT_2301 (Target 50μm)

Figure 3-2 Photograph of Delidded and Thinned DAC39RF10-SP Sitting in the RF Test Socket