SBAK043 April   2026 DAC39RF10-SP , DAC39RFS10-SP

 

  1.   1
  2.   2
  3.   Trademarks
  4. 1Introduction
  5. 2Single-Event Effects
  6. 3Device and Test Board Information
  7. 4Irradiation Facility and Setup
  8. 5Test Setup and Procedures
  9. 6Single-Event Latch-Up (SEL) Results
  10. 7Single-Event Functional Interrupt (SEFI) Results
    1. 7.1 Converter Performance and Digital (DUC + JESD204C Link) Hardness
    2. 7.2 Configuration Register Hardness
    3. 7.3 SPI Programming During Irradiation
  11. 8SEU Results
    1. 8.1 JESD204C Link Monitoring Results
    2. 8.2 Digital Up-Converter and NCO Upset Recovery
    3. 8.3 Estimating Upset Rates in Unprotected Data Paths
    4. 8.4 Event Rate Calculations
    5. 8.5 Summary of Radiation Hardness
  12. 9References
  13.   A Appendix: Recommendations for Hi-Rel Systems
    1.     A.1 Summary of Rad-Hard Design Features
    2.     A.2 SPI Programming
    3.     A.3 JESD204C Reliability
    4.     A.4 Equalizer Usage in Radiation Environments
    5.     A.5 NCO Reliability
    6.     A.6 NCO Frequency and Phase Correction (Strategy #1)
    7.     A.7 NCO Frequency Correction (Strategy #2)
    8.     A.8 NCO Self-Sync/Self-Coherent Mode (Strategy #3)

2 Single-Event Effects

The primary concern of interest for the DAC39RF10-SP is the robustness against single-event latch-up (SEL) and single-event functional interrupt (SEFI).

In CMOS technologies, such as TI's 40nm CMOS (C014.P) process used on the DAC39RF10-SP, the CMOS circuitry inherently introduces a potential for SEL susceptibility. SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-sub and n-well and n+ and p+ contacts). The parasitic bipolar structure initiated by a single event creates a high-conductance path (inducing a steady-state current that is typically orders of magnitude higher than the normal operating current). This current between power and ground persists or is latched until power is removed, the device is reset, or until the device is destroyed by the high current state. Understanding this concern, a custom PDK with careful layout considerations was made to achieve latch-up immunity in the DAC39RF10-SP compared to the standard C014.P design rules.

The DAC39RF10-SP was tested for SEL using a custom evaluation board which operates the device at maximum recommended power supply voltages. The device exhibits no SEL with heavy ions up to an LETEFF = 120 MeV·cm2/mg at a flux of approximately 105 ions/cm2·s, fluence of approximately 107 ions/cm2, and a die temperature of 125°C, achieved using Au ions.

The DAC39RF10-SP was also monitored for SEUs and SEFIs during every beam run. The DAC39RF10-SP configuration registers are immune to single event upset (SEUs) by employing a proprietary rad-hard flip-flop in the design and the device has been architected, verified, and validated to be SEFI-free up to an LETEFF = 120 MeV·cm2/mg. The device also auto-recovers from any potential SEU due to careful analog and digital design considerations and techniques.