SBAK043 April   2026 DAC39RF10-SP , DAC39RFS10-SP

 

  1.   1
  2.   2
  3.   Trademarks
  4. 1Introduction
  5. 2Single-Event Effects
  6. 3Device and Test Board Information
  7. 4Irradiation Facility and Setup
  8. 5Test Setup and Procedures
  9. 6Single-Event Latch-Up (SEL) Results
  10. 7Single-Event Functional Interrupt (SEFI) Results
    1. 7.1 Converter Performance and Digital (DUC + JESD204C Link) Hardness
    2. 7.2 Configuration Register Hardness
    3. 7.3 SPI Programming During Irradiation
  11. 8SEU Results
    1. 8.1 JESD204C Link Monitoring Results
    2. 8.2 Digital Up-Converter and NCO Upset Recovery
    3. 8.3 Estimating Upset Rates in Unprotected Data Paths
    4. 8.4 Event Rate Calculations
    5. 8.5 Summary of Radiation Hardness
  12. 9References
  13.   A Appendix: Recommendations for Hi-Rel Systems
    1.     A.1 Summary of Rad-Hard Design Features
    2.     A.2 SPI Programming
    3.     A.3 JESD204C Reliability
    4.     A.4 Equalizer Usage in Radiation Environments
    5.     A.5 NCO Reliability
    6.     A.6 NCO Frequency and Phase Correction (Strategy #1)
    7.     A.7 NCO Frequency Correction (Strategy #2)
    8.     A.8 NCO Self-Sync/Self-Coherent Mode (Strategy #3)

5 Test Setup and Procedures

The DAC39RF10-SP was configured as follows for all SEE testing (unless otherwise noted):

  • DACCLK = 10.24GHz from R&S® SGS100A
  • JMODE3, 64b/66b encoding, 8x interpolation, and Subclass 1
  • SerDes rate 10.56Gbps, 16 lanes, 2 lanes per stream (M = 8)
  • NCO set to re-align with SYSREF in Subclass 1 (“Strategy #1”)
  • SYSREF = 5MHz for this configuration (continuous SYSREF from LMK04832)
  • Pattern generator = TSW14J59 Rev C using “6466b 2/11/2022” firmware and TSW_controller_051722 (FPGA reference clock from LMK is 160MHz)
  • A 97MHz tone is sent over the JESD204C link and all four (4) of the DAC39RF10-SP’s NCOs are used to up-convert this tone to 297, 497, 697, and 897MHz, respectively.
  • DAC outputs were monitored with either the ADC12DJ5200RFEVM (making it an effective and low-cost spectrum analyzer), an R&S® FSWP spectrum analyzer, or an oscilloscope with standard triggering functionality.
  • Supplies set to +5% for SEL testing; forced air to achieve Tj > 125℃
  • Supplies set to -5% for SEFI testing; ambient temperature (no forced air)

DAC39RF10 SEE Test Setup Block Diagram

Figure 5-1 DAC39RF10 SEE Test Setup Block Diagram