ZHCSO18A december   2022  – june 2023 TPS281C30

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 SNS Timing Characteristics
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Device Functional Modes
      1. 9.3.1 Working Mode
    4. 9.4 Feature Description
      1. 9.4.1 Accurate Current Sense
        1. 9.4.1.1 High Accuracy Sense Mode
      2. 9.4.2 Programmable Current Limit
        1. 9.4.2.1 Short-Circuit and Overload Protection
        2. 9.4.2.2 Capacitive Charging
      3. 9.4.3 Inductive-Load Switching-Off Clamp
      4. 9.4.4 Inductive Load Demagnetization
      5. 9.4.5 Full Protections and Diagnostics
        1. 9.4.5.1 Open-Load Detection
        2. 9.4.5.2 Thermal Protection Behavior
        3. 9.4.5.3 Undervoltage Lockout (UVLO) Protection
        4. 9.4.5.4 Overvoltage (OVP) Protection
        5. 9.4.5.5 Reverse Polarity Protection
        6. 9.4.5.6 Protection for MCU I/Os
        7. 9.4.5.7 Diagnostic Enable Function
        8. 9.4.5.8 Loss of Ground
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 IEC 61000-4-5 Surge
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Selecting RILIM
        2. 10.2.2.2 Selecting RSNS
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 EMC Considerations
      2. 10.4.2 Layout Example
        1. 10.4.2.1 PWP Layout without a GND Network
        2. 10.4.2.2 PWP Layout with a GND Network
        3. 10.4.2.3 RGW Layout with a GND Network
      3. 10.4.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 静电放电警告
    5. 11.5 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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9.4.3 Inductive-Load Switching-Off Clamp

When an inductive load is switching off, the output voltage is pulled down to negative, due to the inductance characteristics. The power FET may break down if the voltage is not clamped during the current-decay period. To protect the power FET in this situation, internally clamp the drain-to-source voltage, namely VDS,clamp, the clamp diode between the drain and gate.

Equation 3. VDS,Clamp = VS – VOUT

During the current-decay period (TDECAY), the power FET is turned on for inductance-energy dissipation. Both the energy of the power supply (ES) and the load (ELOAD) are dissipated on the high-side power switch itself, which is called EHSD. If resistance is in series with inductance, some of the load energy is dissipated in the resistance.

Equation 4. EHSD = ES + ELOAD = ES + EL – ER

From the high-side power switch’s view, EHSD equals the integration value during the current-decay period.

Equation 5. GUID-6C74955B-CC1D-46B0-A1C2-BC95C123F8BC-low.gif
Equation 6. GUID-326D5FEA-82C7-464D-BFFE-C0CB7315577F-low.gif
Equation 7. GUID-1D6CB3D3-BFDF-4E5C-B7D6-8074A2E53450-low.gif

When R approximately equals 0, EHSD can be given simply as:

Equation 8. GUID-493AA22E-C3D8-451A-A76A-F6C376695533-low.gif
GUID-20210531-CA0I-7XZF-ZBTX-WJJ3TPQRJBBK-low.svg Figure 9-11 Driving Inductive Load
GUID-20210531-CA0I-QV5V-Z76N-XBMKZ7JQTPJJ-low.svgFigure 9-12 Inductive-Load Switching-Off Diagram

As discussed previously, when switching off, battery energy and load energy are dissipated on the high-side power switch, which leads to the large thermal variation. For each high-side power switch, the upper limit of the maximum safe power dissipation depends on the device intrinsic capacity, ambient temperature, and board dissipation condition. TI provides the upper limit of single-pulse energy that devices can tolerate under the test condition: VS = 24 V, inductance from 0.1 mH to 400 mH, R = 0 Ω, FR4 2s2p board, 2× 70-μm copper, 2× 35-μm copper, thermal pad copper area 600 mm2.