ZHCSIP5 August 2018 PGA305
PRODUCTION DATA.
I2C is a synchronous serial communication standard that requires the following two pins for communication:
In addition, the I2CADDR pin is used to select the I2C device address of PGA305. Specifically:
It is noted that for valid I2C communication to occur I2CADDR should not change value during an I2C transaction.
I2C communicates in a master-and-slave style communication bus where one device, the master, can initiate data transmission. The device always acts as the slave device in I2C communication where the external device that communicates to it acts as the master. The master device is responsible for initiating communication over the SDA line and supplying the clock signal on the SCL line. When the I2C SDA line is pulled low, it is considered a logical zero, and when the I2C SDA line is floating high, it is considered a logical one. For the I2C interface to have access to the configuration registers, the IF_SEL and the COMPENSATION_RESET bits in the COMPENSATION_CONTROL register have to be set to logic one.