ZHCSIP5 August   2018 PGA305

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      PAG305 简化方框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics – Reverse Voltage Protection
    6. 6.6  Electrical Characteristics – Regulators
    7. 6.7  Electrical Characteristics – Internal Reference
    8. 6.8  Electrical Characteristics – Bridge Sensor Supply
    9. 6.9  Electrical Characteristics – Temperature Sensor Supply
    10. 6.10 Electrical Characteristics – Internal Temperature Sensor
    11. 6.11 Electrical Characteristics – P Gain (Chopper Stabilized)
    12. 6.12 Electrical Characteristics – P Analog-to-Digital Converter
    13. 6.13 Electrical Characteristics – T Gain (Chopper Stabilized)
    14. 6.14 Electrical Characteristics – T Analog-to-Digital Converter
    15. 6.15 Electrical Characteristics – One-Wire Interface
    16. 6.16 I2C Interface
    17. 6.17 Electrical Characteristics – DAC Output
    18. 6.18 Electrical Characteristics – DAC Gain
    19. 6.19 Electrical Characteristics – Non-Volatile Memory
    20. 6.20 Electrical Characteristics – Diagnostics
    21. 6.21 Operating Characteristics
    22. 6.22 I2C Interface Timing Requirements
    23. 6.23 Timing Diagram
    24. 6.24 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reverse-Voltage Protection Block
      2. 7.3.2  Linear Regulators
      3. 7.3.3  Internal Reference
        1. 7.3.3.1 High-Voltage Reference
        2. 7.3.3.2 Accurate Reference
      4. 7.3.4  BRG+ to BRG– Supply for the Resistive Bridge
      5. 7.3.5  ITEMP Supply for the Temperature Sensor
      6. 7.3.6  Internal Temperature Sensor
      7. 7.3.7  P Gain
      8. 7.3.8  P Analog-to-Digital Converter
        1. 7.3.8.1 P Sigma-Delta Modulator for P ADC
        2. 7.3.8.2 P Decimation Filter for P ADC
      9. 7.3.9  T Gain
      10. 7.3.10 T Analog-to-Digital Converter
        1. 7.3.10.1 T Sigma-Delta Modulator for T ADC
        2. 7.3.10.2 T Decimation Filters for T ADC
      11. 7.3.11 P GAIN and T GAIN Calibration
      12. 7.3.12 One-Wire Interface (OWI)
        1. 7.3.12.1 Overview of OWI
        2. 7.3.12.2 Activating and Deactivating the OWI Interface
          1. 7.3.12.2.1 Activating OWI Communication
          2. 7.3.12.2.2 Deactivating OWI Communication
        3. 7.3.12.3 OWI Protocol
          1. 7.3.12.3.1 OWI Frame Structure
            1. 7.3.12.3.1.1 Standard Field Structure
            2. 7.3.12.3.1.2 Frame Structure
            3. 7.3.12.3.1.3 Sync Field
            4. 7.3.12.3.1.4 Command Field
            5. 7.3.12.3.1.5 Data Fields
          2. 7.3.12.3.2 OWI Commands
            1. 7.3.12.3.2.1 OWI Write Command
            2. 7.3.12.3.2.2 OWI Read Initialization Command
            3. 7.3.12.3.2.3 OWI Read-Response Command
            4. 7.3.12.3.2.4 OWI Burst-Write Command (EEPROM Cache Access)
            5. 7.3.12.3.2.5 OWI Burst Read Command (EEPROM Cache Access)
          3. 7.3.12.3.3 OWI Operations
            1. 7.3.12.3.3.1 Write Operation
            2. 7.3.12.3.3.2 Read Operation
            3. 7.3.12.3.3.3 EEPROM Burst Write
            4. 7.3.12.3.3.4 EEPROM Burst Read
        4. 7.3.12.4 OWI Communication-Error Status
      13. 7.3.13 I2C Interface
        1. 7.3.13.1 Overview of I2C Interface
        2. 7.3.13.2 Clocking Details of I2C Interface
        3. 7.3.13.3 I2C Interface Protocol
        4. 7.3.13.4 PGA305 I2C Runtime Commands
        5. 7.3.13.5 PGA305 I2C Transfer Example
      14. 7.3.14 DAC Output
        1. 7.3.14.1 Ratiometric vs Absolute
      15. 7.3.15 DAC Gain
      16. 7.3.16 Memory
        1. 7.3.16.1 EEPROM Memory
          1. 7.3.16.1.1 EEPROM Cache
          2. 7.3.16.1.2 EEPROM Programming Procedure
          3. 7.3.16.1.3 EEPROM Programming Current
          4. 7.3.16.1.4 CRC
        2. 7.3.16.2 Control and Status Registers Memory
      17. 7.3.17 Diagnostics
        1. 7.3.17.1 Power Supply Diagnostics
        2. 7.3.17.2 Signal Chain Faults
          1. 7.3.17.2.1 P Gain and T Gain Input Faults
          2. 7.3.17.2.2 P Gain and T Gain Output Diagnostics
          3. 7.3.17.2.3 Masking Signal Chain Faults
          4. 7.3.17.2.4 Fault Detection Timing
      18. 7.3.18 Reading Diagnostics Information Through I2C
      19. 7.3.19 Digital Compensation and Filter
        1. 7.3.19.1 Digital Gain and Offset
        2. 7.3.19.2 TC and NL Correction
          1. 7.3.19.2.1 TC and NL Coefficients
            1. 7.3.19.2.1.1 No TC and NL Coefficients
          2. 7.3.19.2.2 TC Compensation Using the Internal Temperature Sensor
        3. 7.3.19.3 Clamping
        4. 7.3.19.4 Filter
      20. 7.3.20 Filter Coefficients
        1. 7.3.20.1 No Filtering
        2. 7.3.20.2 Filter Coefficients for P ADC Sampling Rate = 1024 µs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage Mode
      2. 7.4.2 Current Mode
    5. 7.5 Register Maps
      1. 7.5.1 Register Settings
      2. 7.5.2 Control and Status Registers
        1. 7.5.2.1  Digital Interface Control (M0 Address = 0x40000506) (DI Page Address = 0x2) (DI Page Offset = 0x06)
        2. 7.5.2.2  DAC_CTRL_STATUS (M0 Address: 0x40000538) (DI Page Address: 0x2) (DI Page Offset: 0x38)
        3. 7.5.2.3  DAC_CONFIG (EEPROM Address = 0x40000032) (DI Page Address: 0x2) (DI Page Offset: 0x39)
        4. 7.5.2.4  OP_STAGE_CTRL (EEPROM Address = 0x40000033) (DI Page Address: 0x2) (DI Page Offset: 0x3B)
        5. 7.5.2.5  BRDG_CTRL (EEPROM Address = 0x40000034) (DI Page Address: 0x2) (DI Page Offset: 0x46)
        6. 7.5.2.6  P_GAIN_SELECT (EEPROM Address = 0x40000035) (DI Page Address: 0x2) (DI Page Offset: 0x47)
        7. 7.5.2.7  T_GAIN_SELECT (EEPROM Address = 0x40000036) (DI Page Address: 0x2) (DI Page Offset: 0x48)
        8. 7.5.2.8  TEMP_CTRL (EEPROM Address = 0x40000037) (DI Page Address: 0x2) (DI Page Offset: 0x4C)
        9. 7.5.2.9  TEMP_SE (EEPROM Address = 0x4000003A)
        10. 7.5.2.10 DIAG_ENABLE (EEPROM Address = 0x40000056)
        11. 7.5.2.11 EEPROM_LOCK (EEPROM Address = 0x40000057)
        12. 7.5.2.12 AFEDIAG_CFG (EEPROM Address = 0x40000058)
        13. 7.5.2.13 AFEDIAG_MASK (EEPROM Address = 0x40000059)
        14. 7.5.2.14 ADC_24BIT_ENABLE (EEPROM Address = 0x40000068)
        15. 7.5.2.15 OFFSET_ENABLE (EEPROM Address = 0x40000069)
        16. 7.5.2.16 COMPENSATION_CONTROL (EEPROM Address = N/A) (DI Page Address: 0x0) (DI Page Offset: 0x0C)
        17. 7.5.2.17 EEPROM_PAGE_ADDRESS (EEPROM Address = N/A) (DI Page Address: 0x5) (DI Page Offset: 0x88)
        18. 7.5.2.18 EEPROM_CTRL (EEPROM Address = N/A) (DI Page Address: 0x5) (DI Page Offset: 0x89)
        19. 7.5.2.19 EEPROM_CRC (EEPROM Address = N/A) (DI Page Address: 0x5) (DI Page Offset: 0x8A)
        20. 7.5.2.20 EEPROM_STATUS (EEPROM Address = N/A) (DI Page Address: 0x5) (DI Page Offset: 0x8B)
        21. 7.5.2.21 EEPROM_CRC_STATUS (EEPROM Address = N/A) (DI Page Address: 0x5) (DI Page Offset: 0x8C)
        22. 7.5.2.22 EEPROM_CRC_VALUE (EEPROM Address = 0x4000007F) (DI Page Address: 0x5) (DI Page Offset: 0x8D)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 4-mA to 20-mA Output With Internal Sense Resistor
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calibration Tips
            1. 8.2.1.2.1.1 Programming the EEPROM for 4-mA to 20-mA Output
        3. 8.2.1.3 Application Curve
      2. 8.2.2 0- to 10-V Absolute Output With Internal Drive
        1. 8.2.2.1 Design Requirements
      3. 8.2.3 0- to 5-V Ratiometric Output With Internal Drive
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 Programmer Tips
            1. 8.2.3.2.1.1 Resetting the Microprocessor and Enable Digital Interface
            2. 8.2.3.2.1.2 Turning On the Accurate Reference Buffer (REFCAP Voltage)
            3. 8.2.3.2.1.3 Turning On DAC and DAC GAIN
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5.2 Control and Status Registers

Table 20. Control and Status Registers

Register Name DI Page Address DI Offset Address EEPROM Address R/W D7 D6 D5 D4 D3 D2 D1 D0
H0_LSB N/A N/A 0x40000000 RW H0 [7] H0 [6] H0 [5] H0 [4] H0 [3] H0 [2] H0 [1] H0 [0]
H0_MID N/A N/A 0x40000001 RW H0 [15] H0 [14] H0 [13] H0 [12] H0 [11] H0 [10] H0 [9] H0 [8]
H0_MSB N/A N/A 0x40000002 RW H0 [23] - SIGN H0 [22] H0 [21] H0 [20] H0 [19] H0 [18] H0 [17] H0 [16]
H1_LSB N/A N/A 0x40000003 RW H1 [7] H1 [6] H1 [5] H1 [4] H1 [3] H1 [2] H1 [1] H1 [0]
H1_MID N/A N/A 0x40000004 RW H1 [15] H1 [14] H1 [13] H1 [12] H1 [11] H1 [10] H1 [9] H1 [8]
H1_MSB N/A N/A 0x40000005 RW H1 [23] - SIGN H1 [22] H1 [21] H1 [20] H1 [19] H1 [18] H1 [17] H1 [16]
H2_LSB N/A N/A 0x40000006 RW H2 [7] H2 [6] H2 [5] H2 [4] H2 [3] H2 [2] H2 [1] H2 [0]
H2_MID N/A N/A 0x40000007 RW H2 [15] H2 [14] H2 [13] H2 [12] H2 [11] H2 [10] H2 [9] H2 [8]
H2_MSB N/A N/A 0x40000008 RW H2 [23] - SIGN H2 [22] H2 [21] H2 [20] H2 [19] H2 [18] H2 [17] H2 [16]
H3_LSB N/A N/A 0x40000009 RW H3 [7] H3 [6] H3 [5] H3 [4] H3 [3] H3 [2] H3 [1] H3 [0]
H3_MID N/A N/A 0x4000000A RW H3 [15] H3 [14] H3 [13] H3 [12] H3[11] H3 [10] H3 [9] H3 [8]
H3_MSB N/A N/A 0x4000000B RW H3 [23] - SIGN H3 [22] H3 [21] H3 [20] H3 [19] H3 [18] H3 [17] H3 [16]
G0_LSB N/A N/A 0x4000000C RW G0 [7] G0 [6] G0 [5] G0 [4] G0 [3] G0 [2] G0 [1] G0 [0]
G0_MID N/A N/A 0x4000000D RW G0 [15] G0 [14] G0 [13] G0 [12] G0 [11] G0 [10] G0 [9] G0 [8]
G0_MSB N/A N/A 0x4000000E RW G0 [23] - SIGN G0 [22] G0 [21] G0 [20] G0 [19] G0 [18] G0 [17] G0 [16]
G1_LSB N/A N/A 0x4000000F RW G1 [7] G1 [6] G1 [5] G1 [4] G1 [3] G1 [2] G1 [1] G1 [0]
G1_MID N/A N/A 0x40000010 RW G1 [15] G1 [14] G1 [13] G1 [12] G1 [11] G1 [10] G1 [9] G1 [8]
G1_MSB N/A N/A 0x40000011 RW G1 [23] - SIGN G1 [22] G1 [21] G1 [20] G1 [19] G1 [18] G1 [17] G1 [16]
G2_LSB N/A N/A 0x40000012 RW G2 [7] G2 [6] G2 [5] G2 [4] G2 [3] G2 [2] G2 [1] G2 [0]
G2_MID N/A N/A 0x40000013 RW G2 [15] G2 [14] G2 [13] G2 [12] G2 [11] G2 [10] G2 [9] G2 [8]
G2_MSB N/A N/A 0x40000014 RW G2 [23] - SIGN G2 [22] G2 [21] G2 [20] G2 [19] G2 [18] G2 [17] G2 [16]
G3_LSB N/A N/A 0x40000015 RW G3 [7] G3 [6] G3 [5] G3 [4] G3 [3] G3 [2] G3 [1] G3 [0]
G3_MID N/A N/A 0x40000016 RW G3 [15] G3 [14] G3 [13] G3 [12] G3[11] G3 [10] G3 [9] G3 [8]
G3_MSB N/A N/A 0x40000017 RW G3 [23] - SIGN G3 [22] G3 [21] G3 [20] G3 [19] G3 [18] G3 [17] G3 [16]
N0_LSB N/A N/A 0x40000018 RW N0 [7] N0 [6] N0 [5] N0 [4] N0 [3] N0 [2] N0 [1] N0 [0]
N0_MID N/A N/A 0x40000019 RW N0 [15] N0 [14] N0 [13] N0 [12] N0 [11] N0 [10] N0 [9] N0 [8]
N0_MSB N/A N/A 0x4000001A RW N0 [23] - SIGN N0 [22] N0 [21] N0 [20] N0 [19] N0 [18] N0 [17] N0 [16]
N1_LSB N/A N/A 0x4000001B RW N1 [7] N1 [6] N1 [5] N1 [4] N1 [3] N1 [2] N1 [1] N1 [0]
N1_MID N/A N/A 0x4000001C RW N1 [15] N1 [14] N1 [13] N1 [12] N1 [11] N1 [10] N1 [9] N1 [8]
N1_MSB N/A N/A 0x4000001D RW N1 [23] - SIGN N1 [22] N1 [21] N1 [20] N1 [19] N1 [18] N1 [17] N1 [16]
N2_LSB N/A N/A 0x4000001E RW N2 [7] N2 [6] N2 [5] N2 [4] N2 [3] N2 [2] N2 [1] N2 [0]
N2_MID N/A N/A 0x4000001F RW N2 [15] N2 [14] N2 [13] N2 [12] N2 [11] N2 [10] N2 [9] N2 [8]
N2_MSB N/A N/A 0x40000020 RW N2 [23] - SIGN N2 [22] N2 [21] N2 [20] N2 [19] N2 [18] N2 [17] N2 [16]
N3_LSB N/A N/A 0x40000021 RW N3 [7] N3 [6] N3 [5] N3 [4] N3 [3] N3 [2] N3 [1] N3 [0]
N3_MID N/A N/A 0x40000022 RW N3 [15] N3 [14] N3 [13] N3 [12] N3[11] N3 [10] N3 [9] N3 [8]
N3_MSB N/A N/A 0x40000023 RW N3 [23] - SIGN N3 [22] N3 [21] N3 [20] N3 [19] N3 [18] N3 [17] N3 [16]
M0_LSB N/A N/A 0x40000024 RW M0 [7] M0 [6] M0 [5] M0 [4] M0 [3] M0 [2] M0 [1] M0 [0]
M0_MID N/A N/A 0x40000025 RW M0 [15] M0 [14] M0 [13] M0 [12] M0 [11] M0 [10] M0 [9] M0 [8]
M0_MSB N/A N/A 0x40000026 RW M0 [23] - SIGN M0 [22] M0 [21] M0 [20] M0 [19] M0 [18] M0 [17] M0 [16]
M1_LSB N/A N/A 0x40000027 RW M1 [7] M1 [6] M1 [5] M1 [4] M1 [3] M1 [2] M1 [1] M1 [0]
M1_MID N/A N/A 0x40000028 RW M1 [15] M1 [14] M1 [13] M1 [12] M1 [11] M1 [10] M1 [9] M1 [8]
M1_MSB N/A N/A 0x40000029 RW M1 [23] - SIGN M1 [22] M1 [21] M1 [20] M1 [19] M1 [18] M1 [17] M1 [16]
M2_LSB N/A N/A 0x4000002A RW M2 [7] M2 [6] M2 [5] M2 [4] M2 [3] M2 [2] M2 [1] M2 [0]
M2_MID N/A N/A 0x4000002B RW M2 [15] M2 [14] M2 [13] M2 [12] M2 [11] M2 [10] M2 [9] M2 [8]
M2_MSB N/A N/A 0x4000002C RW M2 [23] - SIGN M2 [22] M2 [21] M2 [20] M2 [19] M2 [18] M2 [17] M2 [16]
M3_LSB N/A N/A 0x4000002D RW M3 [7] M3 [6] M3 [5] M3 [4] M3 [3] M3 [2] M3 [1] M3 [0]
M3_MID N/A N/A 0x4000002E RW M3 [15] M3 [14] M3 [13] M3 [12] M3[11] M3 [10] M3 [9] M3 [8]
M3_MSB N/A N/A 0x4000002F RW M3 [23] - SIGN M3 [22] M3 [21] M3 [20] M3 [19] M3 [18] M3 [17] M3 [16]
DIG_IF_CTRL N/A N/A 0x40000030 RW I2C_
DEGLITCH_
EN		 I2C_RATE Reserved Reserved Reserved I2C_EN Reserved
PADC_DATA1 0x2 0x20 N/A R PADC_DATA[7] PADC_DATA[6] PADC_DATA[5] PADC_DATA[4] PADC_DATA[3] PADC_DATA[2] PADC_DATA[1] PADC_DATA[0]
PADC_DATA2 0x2 0x21 N/A R PADC_DATA[15] PADC_DATA[14] PADC_DATA[13] PADC_DATA[12] PADC_DATA[11] PADC_DATA[10] PADC_DATA[9] PADC_DATA[8]
PADC_DATA3 0x2 0x22 N/A R PADC_DATA_SIGN PADC_DATA[22] PADC_DATA[21] PADC_DATA[20] PADC_DATA[19] PADC_DATA[18] PADC_DATA[17] PADC_DATA[16]
TADC_DATA1 0x2 0x24 N/A R TADC_DATA[7] TADC_DATA[6] TADC_DATA[5] TADC_DATA[4] TADC_DATA[3] TADC_DATA[2] TADC_DATA[1] TADC_DATA[0]
TADC_DATA2 0x2 0x25 N/A R TADC_DATA[15] TADC_DATA[14] TADC_DATA[13] TADC_DATA[12] TADC_DATA[11] TADC_DATA[10] TADC_DATA[9] TADC_DATA[8]
TADC_DATA3 0x2 0x26 N/A R TADC_DATA_SIGN TADC_DATA[22] TADC_DATA[21] TADC_DATA[20] TADC_DATA[19] TADC_DATA[18] TADC_DATA[17] TADC_DATA[16]
DAC_REG0_1 0x2 0x30 N/A RW DAC_REG0[7] DAC_REG0[6] DAC_REG0[5] DAC_REG0[4] DAC_REG0[3] DAC_REG0[2] DAC_REG0[1] DAC_REG0[0]
DAC_REG0_2 0x2 0x31 N/A RW DAC_REG0[13] DAC_REG0[12] DAC_REG0[11] DAC_REG0[10] DAC_REG0[9] DAC_REG0[8]
DAC_CTRL_
STATUS		 0x2 0x38 0x40000031 RW DAC_
ENABLE
DAC_CONFIG 0x2 0x39 0x40000032 RW DAC_
RATIOMETRIC
OP_STAGE_CTRL 0x2 0x3B 0x40000033 RW DACCAP_EN 4_20MA_EN DAC_GAIN[2] DAC_GAIN[1] DAC_GAIN[0]
BRDG_CTRL 0x2 0x46 0x40000034 RW VBRDG_
CTRL[1] 		VBRDG_
CTRL[0]		 BRDG_EN
P_GAIN_
SELECT 		0x2 0x47 0x40000035 RW P_INV P_GAIN[4] P_GAIN[3] P_GAIN[2] P_GAIN[1] P_GAIN[0]
T_GAIN_
SELECT 		0x2 0x48 0x40000036 RW T_INV T_GAIN[1] T_GAIN[0]
TEMP_CTRL 0x2 0x4C 0x40000037 RW ITEMP_
CTRL[2] 		ITEMP_
CTRL[1] 		ITEMP_
CTRL[0] 		TEMP_MUX_
CTRL[3] 		TEMP_MUX_
CTRL[2] 		TEMP_MUX_
CTRL[1] 		TEMP_MUX_
CTRL[0]
TEMP_SE N/A N/A 0x4000003A RW TEMP_SE
NORMAL_LOW_LSB N/A N/A 0x4000003C RW NORMAL_LOW[7] NORMAL_LOW[6] NORMAL_LOW[5] NORMAL_LOW[4] NORMAL_LOW[3] NORMAL_LOW[2] NORMAL_LOW[1] NORMAL_LOW[0]
NORMAL_LOW_MSB N/A N/A 0x4000003D RW NORMAL_LOW[15] NORMAL_LOW[14] NORMAL_LOW[13] NORMAL_LOW[12] NORMAL_LOW[11] NORMAL_LOW[10] NORMAL_LOW[9] NORMAL_LOW[8]
NORMAL_HIGH_LSB N/A N/A 0x4000003E RW NORMAL_HIGH[7] NORMAL_HIGH[6] NORMAL_HIGH[5] NORMAL_HIGH[4] NORMAL_HIGH[3] NORMAL_HIGH[2] NORMAL_HIGH[1] NORMAL_HIGH[0]
NORMAL_HIGH_MSB N/A N/A 0x4000003F RW NORMAL_HIGH[15] NORMAL_HIGH[14] NORMAL_HIGH[13] NORMAL_HIGH[12] NORMAL_HIGH[11] NORMAL_HIGH[10] NORMAL_HIGH[9] NORMAL_HIGH[8]
LOW_CLAMP_LSB N/A N/A 0x40000040 RW LOW_CLAMP[7] LOW_CLAMP[6] LOW_CLAMP[5] LOW_CLAMP[4] LOW_CLAMP[3] LOW_CLAMP[2] LOW_CLAMP[1] LOW_CLAMP[0]
LOW_CLAMP_MSB N/A N/A 0x40000041 RW LOW_CLAMP[15] LOW_CLAMP[14] LOW_CLAMP[13] LOW_CLAMP[12] LOW_CLAMP[11] LOW_CLAMP[10] LOW_CLAMP[9] LOW_CLAMP[8]
HIGH_CLAMP_LSB N/A N/A 0x40000042 RW HIGH_CLAMP[7] HIGH_CLAMP[6] HIGH_CLAMP[5] HIGH_CLAMP[4] HIGH_CLAMP[3] HIGH_CLAMP[2] HIGH_CLAMP[1] HIGH_CLAMP[0]
HIGH_CLAMP_MSB N/A N/A 0x40000043 RW HIGH_CLAMP[15] HIGH_CLAMP[14] HIGH_CLAMP[13] HIGH_CLAMP[12] HIGH_CLAMP[11] HIGH_CLAMP[10] HIGH_CLAMP[9] HIGH_CLAMP[8]
PADC_GAIN_LSB N/A N/A 0x40000044 RW PADC_GAIN[7] PADC_GAIN[6] PADC_GAIN[5] PADC_GAIN[4] PADC_GAIN[3] PADC_GAIN[2] PADC_GAIN[1] PADC_GAIN[0]
PADC_GAIN_MID N/A N/A 0x40000045 RW PADC_GAIN[15] PADC_GAIN[14] PADC_GAIN[13] PADC_GAIN[12] PADC_GAIN[11] PADC_GAIN[10] PADC_GAIN[9] PADC_GAIN[8]
PADC_GAIN_MSB N/A N/A 0x40000046 RW PADC_GAIN_SIGN PADC_GAIN[22] PADC_GAIN[21] PADC_GAIN[20] PADC_GAIN[19] PADC_GAIN[18] PADC_GAIN[17] PADC_GAIN[16]
PADC_OFFSET_LSB N/A N/A 0x40000047 RW PADC_OFFSET[7] PADC_OFFSET[6] PADC_OFFSET[5] PADC_OFFSET[4] PADC_OFFSET[3] PADC_OFFSET[2] PADC_OFFSET[1] PADC_OFFSET[0]
PADC_GAIN_MID N/A N/A 0x40000048 RW PADC_OFFSET[15] PADC_OFFSET[14] PADC_OFFSET[13] PADC_OFFSET[12] PADC_OFFSET[11] PADC_OFFSET[10] PADC_OFFSET[9] PADC_OFFSET[8]
PADC_OFFSET_MSB N/A N/A 0x40000049 RW PADC_OFFSET_SIGN PADC_OFFSET[22] PADC_OFFSET[21] PADC_OFFSET[20] PADC_OFFSET[19] PADC_OFFSET[18] PADC_OFFSET[17] PADC_OFFSET[16]
A0_LSB N/A N/A 0x4000004A RW IIR_FILT_A0[7] IIR_FILT_A0[6] IIR_FILT_A0[5] IIR_FILT_A0[4] IIR_FILT_A0[3] IIR_FILT_A0[2] IIR_FILT_A0[1] IIR_FILT_A0[0]
A0_MSB N/A N/A 0x4000004B RW IIR_FILT_A0[15] IIR_FILT_A0[14] IIR_FILT_A0[13] IIR_FILT_A0[12] IIR_FILT_A0[11] IIR_FILT_A0[10] IIR_FILT_A0[9] IIR_FILT_A0[8]
A1_LSB N/A N/A 0x4000004C RW IIR_FILT_A1[7] IIR_FILT_A1[6] IIR_FILT_A1[5] IIR_FILT_A1[4] IIR_FILT_A1[3] IIR_FILT_A1[2] IIR_FILT_A1[1] IIR_FILT_A1[0]
A1_MSB N/A N/A 0x4000004D RW IIR_FILT_SIGN IIR_FILT_A1[14] IIR_FILT_A1[13] IIR_FILT_A1[12] IIR_FILT_A1[11] IIR_FILT_A1[10] IIR_FILT_A1[9] IIR_FILT_A1[8]
A2_LSB N/A N/A 0x4000004E RW IIR_FILT_A2[7] IIR_FILT_A2[6] IIR_FILT_A2[5] IIR_FILT_A2[4] IIR_FILT_A2[3] IIR_FILT_A2[2] IIR_FILT_A2[1] IIR_FILT_A2[0]
A2_MSB N/A N/A 0x4000004F RW IIR_FILT_A2[15] IIR_FILT_A2[14] IIR_FILT_A2[13] IIR_FILT_A2[12] IIR_FILT_A2[11] IIR_FILT_A2[10] IIR_FILT_A2[9] IIR_FILT_A2[8]
B0_LSB N/A N/A 0x40000050 RW IIR_FILT_B0[7] IIR_FILT_B0[6] IIR_FILT_B0[5] IIR_FILT_B0[4] IIR_FILT_B0[3] IIR_FILT_B0[2] IIR_FILT_B0[1] IIR_FILT_B0[0]
B0_MSB N/A N/A 0x40000051 RW IIR_FILT_B0[15] IIR_FILT_B0[14] IIR_FILT_B0[13] IIR_FILT_B0[12] IIR_FILT_B0[11] IIR_FILT_B0[10] IIR_FILT_B0[9] IIR_FILT_B0[8]
B1_LSB N/A N/A 0x40000052 RW IIR_FILT_B1[7] IIR_FILT_B1[6] IIR_FILT_B1[5] IIR_FILT_B1[4] IIR_FILT_B1[3] IIR_FILT_B1[2] IIR_FILT_B1[1] IIR_FILT_B1[0]
B1_MSB N/A N/A 0x40000053 RW IIR_FILT_B1[15] IIR_FILT_B1[14] IIR_FILT_B1[13] IIR_FILT_B1[12] IIR_FILT_B1[11] IIR_FILT_B1[10] IIR_FILT_B1[9] IIR_FILT_B1[8]
B2_LSB N/A N/A 0x40000054 RW IIR_FILT_B2[7] IIR_FILT_B2[6] IIR_FILT_B2[5] IIR_FILT_B2[4] IIR_FILT_B2[3] IIR_FILT_B2[2] IIR_FILT_B2[1] IIR_FILT_B2[0]
B2_MSB N/A N/A 0x40000055 RW IIR_FILT_B2[15] IIR_FILT_B2[14] IIR_FILT_B2[13] IIR_FILT_B2[12] IIR_FILT_B2[11] IIR_FILT_B2[10] IIR_FILT_B2[9] IIR_FILT_B2[8]
DIAG_ENABLE N/A N/A 0x40000056 RW DIAG_ENABLE
EEPROM_LOCK N/A N/A 0x40000057 RW EEPROM_LOCK
AFEDIAG_CFG N/A N/A 0x40000058 RW - DIS_R_T DIS_R_P THRS[2] THRS[1] THRS[0] PD2 PD1
AFEDIAG_MASK N/A N/A 0x40000059 RW TGAIN_UV TGAIN_OV PGAIN_UV PGAIN_OV - INT_OV INP_UV INP_OV
FAULT_LSB N/A N/A 0x4000005C RW
FAULT_MSB N/A N/A 0x4000005D RW
TADC_GAIN_LSB N/A N/A 0x4000005E RW TADC_GAIN[7] TADC_GAIN[6] TADC_GAIN[5] TADC_GAIN[4] TADC_GAIN[3] TADC_GAIN[2] TADC_GAIN[1] TADC_GAIN[0]
TADC_GAIN_MID N/A N/A 0x4000005F RW TADC_GAIN[15] TADC_GAIN[14] TADC_GAIN[13] TADC_GAIN[12] TADC_GAIN[11] TADC_GAIN[10] TADC_GAIN[9] TADC_GAIN[8]
TADC_GAIN_MSB N/A N/A 0x40000060 RW TADC_GAIN_SIGN TADC_GAIN[22] TADC_GAIN[21] TADC_GAIN[20] TADC_GAIN[19] TADC_GAIN[18] TADC_GAIN[17] TADC_GAIN[16]
TADC_OFFSET_LSB N/A N/A 0x40000061 RW TADC_OFFSET[7] TADC_OFFSET[6] TADC_OFFSET[5] TADC_OFFSET[4] TADC_OFFSET[3] TADC_OFFSET[2] TADC_OFFSET[1] TADC_OFFSET[0]
TADC_OFFSET_MID N/A N/A 0x40000062 RW TADC_OFFSET[15] TADC_OFFSET[14] TADC_OFFSET[13] TADC_OFFSET[12] TADC_OFFSET[11] TADC_OFFSET[10] TADC_OFFSET[9] TADC_OFFSET[8]
TADC_OFFSET_MSB N/A N/A 0x40000063 RW TADC_OFFSET_SIGN TADC_OFFSET[22] TADC_OFFSET[21] TADC_OFFSET[20] TADC_OFFSET[19] TADC_OFFSET[18] TADC_OFFSET[17] TADC_OFFSET[16]
SERIAL_NUMBER_BYTE0 N/A N/A 0x40000064 RW
SERIAL_NUMBER_BYTE1 N/A N/A 0x40000065 RW
SERIAL_NUMBER_BYTE2 N/A N/A 0x40000066 RW
SERIAL_NUMBER_BYTE3 N/A N/A 0x40000067 RW
ADC_24BIT_ENABLE N/A N/A 0x40000068 RW ADC_24BIT_EN
OFFSET_ENABLE N/A N/A 0x40000069 RW OFF_EN
EEPROM_CRC
_VALUE		 0x5 0x8D 0x4000007F R EEPROM_CRC[7] EEPROM_CRC[6] EEPROM_CRC[5] EEPROM_CRC[4] EEPROM_CRC[3] EEPROM_CRC[2] EEPROM_CRC[1] EEPROM_CRC[0]
COMPENSATION_
CONTROL		 0x0 0x0C N/A RW COMPENSATION_RESET IF_SEL
EEPROM ARRAY 0x5 0x00-0x7F N/A RW
EEPROM_CACHE 0x5 0x80-0x87 N/A RW
EEPROM_PAGE_
ADDRESS		 0x5 0x88 N/A RW ADDR[2] ADDR[1] ADDR[0]
EEPROM_CTRL 0x5 0x89 N/A RW FIXED_
ERASE_
PROG_TIME		 ERASE_AND
_PROGRAM		 ERASE PROGRAM
EEPROM_CRC 0x5 0x8A N/A RW CALCULATE
_CRC
EEPROM_STATUS 0x5 0x8B N/A R PROGRAM_IN
_PROGRESS		 ERASE_IN
_PROGRESS		 READ_IN
_PROGRESS
EEPROM_CRC
_STATUS		 0x5 0x8C N/A R CRC_GOOD CRC_CHECK
_IN_PROG