ZHCSIM2D June   2010  – August 2021 PCM9211

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: General
    6. 6.6  Electrical Characteristics: Analog-to-Digital Converter (ADC)
    7. 6.7  Electrical Characteristics: Digital Audio I/F Receiver (DIR)
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics: ADC
    10. 6.10 Typical Characteristics: ADC Internal Filter
    11. 6.11 Typical Characteristics: ADC Output Spectrum
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Device Comparison
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Audio Interface Receiver (DIR)
      2. 7.3.2 Digital Audio Interface Transmitter (DIT)
      3. 7.3.3 Analog-to-Digital Converter (ADC)
      4. 7.3.4 Auxiliary PCM Audio Input and Output (I/O)
      5. 7.3.5 Routing
      6. 7.3.6 Control Interface
      7. 7.3.7 Multipurpose I/O
      8. 7.3.8 PCM9211 Module Descriptions
        1. 7.3.8.1  Power Supply
        2. 7.3.8.2  Power-Down Function
        3. 7.3.8.3  System Reset
        4. 7.3.8.4  PCM Audio Interface Format
        5. 7.3.8.5  ADC Details
          1. 7.3.8.5.1  System Clock
          2. 7.3.8.5.2  ADC: Clock Source Configuration
          3. 7.3.8.5.3  ADC: Standalone Operation
          4. 7.3.8.5.4  Additional ADC Functions
          5. 7.3.8.5.5  ADC: Power Down and Power Up
          6. 7.3.8.5.6  ADC: Audio Interface Mode and Timing
          7. 7.3.8.5.7  Audio Interface Format
          8. 7.3.8.5.8  ADC and Synchronization with Other Clocks
          9. 7.3.8.5.9  Setting the ADC Sampling Frequency with XTI as Clock Source
          10. 7.3.8.5.10 Analog Inputs to the ADC
          11. 7.3.8.5.11 VCOM Output
          12. 7.3.8.5.12 Oversampling Rate
          13. 7.3.8.5.13 External ADC Mode
          14. 7.3.8.5.14 ADC Level Detect and Interrupt
          15. 7.3.8.5.15 Real World Application
        6. 7.3.8.6  Digital Audio Interface Receiver (Rxin0 To Rxin11)
          1. 7.3.8.6.1  Input Details for Pins Rxin0 through Rxin11
          2. 7.3.8.6.2  PLL Clock Source (Built-In PLL and VCO) Details
          3. 7.3.8.6.3  DIR and PLL Loop Filter Details
          4. 7.3.8.6.4  External (XTI) Clocks, Oscillators, and Supporting Circuitry
          5. 7.3.8.6.5  DIR Data Description
          6. 7.3.8.6.6  Channel Status Data, User Data, and Validity Flag
          7. 7.3.8.6.7  DIR: Parity Error Processing
          8. 7.3.8.6.8  DIR: Errors and Interrupts
          9. 7.3.8.6.9  DIR: Sampling Frequency Calculator for Incoming S/PDIF Inputs
          10. 7.3.8.6.10 DIR: Audio Port Sampling Frequency Calculator
          11. 7.3.8.6.11 Output Register Construction
          12. 7.3.8.6.12 DIR: Auto Source Selector for Main Output and AUX Output
          13. 7.3.8.6.13 Non-PCM Data Detection
          14. 7.3.8.6.14 PC/PD Monitor
        7. 7.3.8.7  Digital Audio Interface Transmitter
          1. 7.3.8.7.1 Overview
          2. 7.3.8.7.2 Selection of DIT Input Source
          3. 7.3.8.7.3 DIT Output Biphase
          4. 7.3.8.7.4 Audio Data and Clock
          5. 7.3.8.7.5 Data Mute Function
          6. 7.3.8.7.6 Channel Status Data
          7. 7.3.8.7.7 User Data
          8. 7.3.8.7.8 Validity Flag
          9. 7.3.8.7.9 Standalone Operation
        8. 7.3.8.8  MPIO Description
          1. 7.3.8.8.1 Overview
          2. 7.3.8.8.2 Assignable Signals for MPIO Pins
          3. 7.3.8.8.3 How to Assign Functions to MPIO
          4. 7.3.8.8.4 Selection of Output Source
          5. 7.3.8.8.5 Assignable Signals to MPO Pins
          6. 7.3.8.8.6 MPIO and MPO Assignments
          7. 7.3.8.8.7 MPIO Description
          8. 7.3.8.8.8 MPIO And MPO Assignment: Pin Assignment Details
        9. 7.3.8.9  Default Routing Function (After Reset)
        10. 7.3.8.10 Multichannel PCM Routing Function
          1. 7.3.8.10.1 Overview
          2. 7.3.8.10.2 Initial Setting
          3. 7.3.8.10.3 Output Source Selection
    4. 7.4 Device Functional Modes
      1. 7.4.1 DSD Input Mode
        1. 7.4.1.1 Typical Register Settings
      2. 7.4.2 Serial Control Mode
      3. 7.4.3 Four-Wire (SPI) Serial Control
        1. 7.4.3.1 Control Data Word Format
        2. 7.4.3.2 Register Write Operation
        3. 7.4.3.3 Register Read Operation
        4. 7.4.3.4 Control Interface Timing Requirements
      4. 7.4.4 Two-Wire (I2C) Serial Control
        1. 7.4.4.1 Slave Address
        2. 7.4.4.2 Packet Protocol
        3. 7.4.4.3 Write Operation
        4. 7.4.4.4 Read Operation
        5. 7.4.4.5 Timing Diagram
    5. 7.5 Register Maps
      1. 7.5.1  Error Output Condition and Shared Port Settings Register (address = 20h) [reset = 00000000]
      2. 7.5.2  DIR Initial Settings Register 1/3 (address: 21h) [reset = 00000000]
      3. 7.5.3  DIR Initial Settings Register 2/3 (address: 22h) [reset = 00000001]
      4. 7.5.4  DIR Initial Settings Register 3/3 (address: 23h) [reset = 00000100]
      5. 7.5.5  Oscillation Circuit Control Register (address: 24h) [reset = 00000000]
      6. 7.5.6  Error Cause Setting Register (address = 25h) [reset = 00000001]
      7. 7.5.7  AUTO Source Selector Cause Setting Register (address = 26h) [reset = 00000001]
      8. 7.5.8  DIR Acceptable fS Range Setting and Mask Register (address: 27h) [reset = 00000000]
      9. 7.5.9  Non-PCM Definition Register (address = 28h) [reset = 00000011]
      10. 7.5.10 DTS-CD/LD Sync Word and Period Detection Setting Register (address: 29h) [reset = 00001100]
      11. 7.5.11 INT0 Output Cause Mask Setting Register (Address: 2Ah) [reset = 11111111]
      12. 7.5.12 INT1 Output Cause Mask Setting Register (Address: 2Bh) [reset = 11111111]
      13. 7.5.13 INT0 Output Register (address = 2Ch) [reset = N/A]
      14. 7.5.14 INT1 Output Register (address = 2Dh) [reset = N/A]
      15. 7.5.15 INT0, INT1 Output Polarity Setting Register (address = 2Eh) [reset = 00000000]
      16. 7.5.16 DIR Output Data Format Register (address = 2Fh) [reset = 00000100]
      17. 7.5.17 DIR Recovered System Clock (SCK) Ratio Setting Register (address = 30h) [reset = 00000010]
      18. 7.5.18 XTI Source, Clock (SCK, BCK, LRCK) Frequency Setting Register (address = 31h) [reset = 00011010]
      19. 7.5.19 DIR Source, Secondary Bit/LR Clock (SBCK/SLRCK) Frequency Setting Register (address = 32h) [reset = 00100010]
      20. 7.5.20 XTI Source, Secondary Bit/LR Clock (SBCK/SLRCK) Frequency Setting Register (address = 33h) [reset = 00100010]
      21. 7.5.21 DIR Input Biphase Source Select, Coax Amplifier Control Register (address = 34h) [reset = 11000010]
      22. 7.5.22 RECOUT0 Output Biphase Source Settings Register (address = 35h) [reset = 00000010]
      23. 7.5.23 RECOUT1 Output Biphase Source Settings Register (address = 36h) [reset = 00000010]
      24. 7.5.24 Port Sampling Frequency Calculator Measurement Target Setting Register (address = 37h) [reset = 00000000]
      25. 7.5.25 Port Sampling Frequency Calculator Result Output Register (address = 38h) [reset = N/A]
      26. 7.5.26 Incoming Biphase Information and Sampling Frequency Register (address = 39h) [reset = N/A]
      27. 7.5.27 PC Buffer (Burst Preamble PC Output) Register (address = 3Ah) [reset = N/A]
      28. 7.5.28 PD Buffer (Burst Preamble PD Output) Register (address = 3Ch) [reset = N/A]
      29. 7.5.29 System Reset Control Register (address = 40h) [reset = 11000000]
      30. 7.5.30 ADC Function Control Register 1/3 (address = 42h) [reset = 00000010]
      31. 7.5.31 ADC L-Ch, Digital ATT Control Register (address = 46h) [reset = 11010111]
      32. 7.5.32 ADC R-Ch, Digital ATT Control Register (address = 47h) [reset = 11010111]
      33. 7.5.33 ADC Function Control Register 2/3 (address = 48h) [reset = 00000000]
      34. 7.5.34 ADC Function Control Register 3/3 (address = 49h) [reset = 00000000]
      35. 7.5.35 DIR Channel Status Data Buffer Register (address = 5Ah) [reset = 00000000]
      36. 7.5.36 DIT Function Control Register 1/3 (address = 60h) [reset = 01000100]
      37. 7.5.37 DIT Function Control Register 2/3 (address = 61h) [reset = 00010000]
      38. 7.5.38 DIT Function Control Register 3/3 (address = 62h) [reset = 00000000]
      39. 7.5.39 DIT Channel Status Data Buffer Register (address = 63h) [reset = 00000000]
      40. 7.5.40 Main Output and AUXOUT Port Control Register (address = 6A) [reset = 00000000]
      41. 7.5.41 Main Output Port (SCKO/BCK/LRCK/DOUT) Source Setting Register (address = 6Bh) [reset = 00000000]
      42. 7.5.42 AUX Output Port (AUXSCKO/AUXBCKO/AUXLRCKO/AUXDOUT) Source Setting Register (address = 6Ch) [reset = 00000000]
      43. 7.5.43 MPIO_B and Main Output Port Hi-Z Control Register (address = 6Dh) [reset = 00000000]
      44. 7.5.44 MPIO_C and MPIO_A Hi-Z Control Register (address = 6Eh) [reset = 00001111]
      45. 7.5.45 MPIO_A, MPIO_B, MPIO_C Group Function Assign Register (address = 6Fh) [reset = 01000000]
      46. 7.5.46 MPIO_A Flags or GPIO Assign Setting Register (address = 70h) [reset = 00000000]
      47. 7.5.47 MPIO_B, MPIO_C Flags or GPIO Assign Setting Register (address = 71h) [reset = 00000000]
      48. 7.5.48 MPIO_A1, MPIO_A0 Output Flag Select Register (address = 72h) [reset = 00000000]
      49. 7.5.49 MPIO_A3, MPIO_A0 Output Flag Select Register (address = 73h) [reset = 00000000]
      50. 7.5.50 MPIO_B1, MPIO_B0 Output Flag Select Register (address = 74h) [reset = 00000000]
      51. 7.5.51 MPIO_B3, MPIO_B2 Output Flag Select Register (address = 75h) [reset = 00000000]
      52. 7.5.52 MPIO_C1, MPIO_C0 Output Flag Select Register (address = 76h) [reset = 00000000]
      53. 7.5.53 MPIO_C3, MPIO_C2 Output Flag Select Register (address = 77h) [reset = 00000000]
      54. 7.5.54 MPO1, MPO0 Function Assign Setting Register (address = 78h) [reset = 00111101]
      55. 7.5.55 GPIO I/O Direction Control for MPIO_A, MPIO_B Register (address = 79h) [reset = 00000000]
      56. 7.5.56 GPIO I/O Direction Control for MPIO_C Register (address = 7Ah) [reset = 00000000]
      57. 7.5.57 GPIO Output Data Setting for MPIO_A, MPIO_B Register (address = 7Bh) [reset = 00000000]
      58. 7.5.58 GPIO Output Data Setting for MPIO_C Register (address = 7Ch) [reset = 00000000]
      59. 7.5.59 GPIO Input Data Register for MPIO_A, MPIO_B Register (address = 7Dh) [reset = N/A]
      60. 7.5.60 GPIO Input Data Register for MPIO_C Register (address = 7Eh) [reset = N/A]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Typical Circuit Connection
      2. 8.1.2 Application Example for Analog Input
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 S/PDIF Ports
        2. 8.2.2.2 PCM Ports
        3. 8.2.2.3 ADC Operation
        4. 8.2.2.4 GPIO/Interrupts
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.3.8.6.4 External (XTI) Clocks, Oscillators, and Supporting Circuitry

An external clock source (CMOS or crystal/resonator) is known as the XTI source. The XTI source can be either a CMOS logic source, or a crystal resonator (internal circuitry in the PCM9211 can start the crystal resonating). Whichever clock source is used, it must be 24.576 MHz.

The PCM9211 uses the XTI source as a reference clock in order to calculate the sampling frequency of the incoming S/PDIF stream. It is also used as the clock source in XTI clock source mode.

When using a resonator as an XTI source, the following points should be considered:

  • The 24.576-MHz resonator should be connected between the XTI and XTO pins
  • The resonator should be a fundamental mode type
  • A crystal or ceramic resonator can be used as the XTI source
  • The values of the load capacitors CL1 and CL2 and the current limiting resistor Rd all depend on the characteristics of the resonator
  • No external feedback resistor between the XTI and XTO pins is required, because the resistor is integrated into the device
  • No loads other than the resonator should be used on the XTO pin

When using an external oscillation circuit with a CMOS output, the following points should be considered:

  • Always supply a 24.576-MHz clock on the XTI pin
  • Only 3.3 V is supported on the XTI pin; 5 V is not supported
  • XTO should be left floating

Figure 7-11 shows the connections for the XTI and XTO pins for both a resonator connection and an external clock input connection.

GUID-F56424AA-9F30-4442-8EFA-586A73ED87E2-low.gifFigure 7-11 XTI and XTO Connection Diagram

In XTI mode, the output clocks (SCKO, BCKO, and LRCKO) are generated from the XTI source clock.

Register 24h/OSCAUTO controls whether or not the internal oscillator functions while it is not required. When using the DIR as a clock source, the XTI source is not required; thus, the internal oscillator can be switched off. There is a constraint, however, that when the DIR wide mode is being set (for example, in 192-kHz support), the XTI is always used. The sampling frequency calculator also requires the XTI source.

XMCKO (the XTI clock buffered output) provides a buffered (and divided) XTI clock that can be output to MPIO_A. Register 24h/XMCKEN controls whether the XMCKO should be muted or not, and Register 24h/XMCKDIV controls the division factor.