ZHCSIM2D June 2010 – August 2021 PCM9211
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | MOSSRC2 | MOSSRC1 | MOSSRC0 | RSV | MOPSRC2 | MOPSRC1 | MOPSRC0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
MOSSRC[2:0]: Main Output Port, SCK Source Control | ||
000: | DIR/ADC Automatic (DIR lock:DIR, DIR unlock:ADC) (default) | |
001: | DIR | |
010: | ADC | |
011: | AUXIN0 | |
100: | AUXIN1 | |
101: | AUXIN2 | |
110: | Reserved | |
111: | Reserved | |
MOPSRC[2:0]: Main Output Port, BCK/LRCK/DATA Source Control | ||
000: | DIR/ADC Automatic (DIR lock:DIR, DIR unlock:ADC) (default) | |
001: | DIR | |
010: | ADC | |
011: | AUXIN0 | |
100: | AUXIN1 | |
101: | AUXIN2 | |
110: | Reserved | |
111: | Reserved |
This source control register is divided into two parts (MOSSRC and MOPSRC). This architecture allows some additional functionality such as jitter cleaning. To clean the clock jitter of the HDMI receiver output, the HDMI receiver S/PDIF output is connected with the PCM9211 S/PDIF input, and the HDMI receiver I2S outputs (BCK/LRCK/DATA) are connected with the PCM9211 PCM input port.