CLKSTCON: CLKST Output Condition Setting |
| 0: | Only PLL Lock status change (default) |
| 1: | All events where the Main port output clock condition changes, as well as these cases: |
| | 1. | MOSSRC/MOPSRC register is updated to ADC, AUXIN0, AUXIN1, or AUXIN2 |
| | 2. | DIR and ADC are switched by DIR status when MOSSRC = 000(AUTO) and MOPSRC = 000(AUTO) |
| | 3. | Main port sampling frequency changes when PFSTGT = 101(Main output port) |
| NOTES: |
| | CLKST never outputs when updating MOSSRC and MOPSRC to AUTO or DIR. |
| | OSCAUTO must be 0 when CLKST is used because CLKST is generated by frequency counting of built-in oscillator circuit. |
| | To output CLKST, MOSSRC and MOPSRC are set simultaneously. |
CLKSTP: CLKST Polarity Setting |
| 0: | Active low (default) |
| 1: | Active high |
RXVDLY: VOUT Delay Setting |
| 0: | VOUT is active immediately after validity flag is detected |
| 1: | VOUT is active after synchronization with DOUT data (default) |