ZHCSIM2D June 2010 – August 2021 PCM9211
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | PSBCK2 | PSBCK1 | PSBCK0 | RSV | PSLRCK2 | PSLRCK1 | PSLRCK0 |
R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
PSBCK[2:0]: DIR Clock Source, Secondary BCK (SBCK) Frequency Setting | ||
000: | 16fS (BCK/4) | |
001: | 32fS (BCK/2) | |
010: | 64fS (1x BCK) (default) | |
011: | 128fS (2x BCK) | |
100: | 256fS (4x BCK) | |
101: | Reserved | |
110: | Reserved | |
111: | Reserved | |
PSLRCK[2:0]: DIR Clock Source, Secondary LRCK (SLRCK) Frequency Setting | ||
000: | fS/4 (LRCK/4) | |
001: | fS/2 (LRCK/2) | |
010: | fS (1x LRCK) (default) | |
011: | 2fS (2x LRCK) | |
100: | 4fS (4x LRCK) | |
101: | Reserved | |
110: | Reserved | |
111: | Reserved |